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preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer pmc-sierra, inc. 105 - 8555 baxter place burnaby, bc canada v5a 4v7 604 .415.6000 PM5366 temap-84 high density 84/63 channel vt/tu mapper and m13 multiplexer datasheet proprietary and confidential preliminary issue 1: april 2001
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential i contents 1 features .............................................................................................. 1 2 applications ..................................................................................... 13 3 references....................................................................................... 14 4 application examples ................................................................... 18 5 block diagram ................................................................................. 21 5.1 top level block diagram .................................................. 21 5.2 ds3/e3 framer only block diagram............................... 22 6 description ...................................................................................... 23 7 pin diagram ....................................................................................... 27 8 pin description................................................................................ 28 9 functional description............................................................... 61 9.1 transparent virtual tributaries ................................. 61 9.2 the tributary indexing ...................................................... 62 9.3 t1 performance monitoring ........................................... 64 9.4 e1 performance monitoring ........................................... 67 9.5 t1/e1 performance data accumulation....................... 73 9.6 t1/e1 hdlc receiver............................................................. 73 9.7 t1/e1 receive and transmit digital jitter attenuators .......................................................................... 74 9.8 t1/e1 pseudo random binary sequence generation and detection (prbs).......................................................... 79 9.9 ds3 framer (ds3-frmr) ....................................................... 79 9.10 ds3 bit oriented code detection .................................. 81
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential ii 9.11 ds3/e3 hdlc receiver (rdlc)............................................. 82 9.12 ds3/e3 performance monitor accumulator (ds3/e3- pmon) ........................................................................................ 82 9.13 ds3 transmitter (ds3-tran).............................................. 83 9.14 ds3/e3 hdlc transmitters ................................................ 85 9.15 ds3 pseudo random pattern generation and detection (prgd).................................................................. 86 9.16 m23 multiplexer (mx23) ....................................................... 86 9.17 ds2 framer (ds2 frmr)........................................................ 87 9.18 m12 multiplexer (mx12) ....................................................... 89 9.19 e3 framer................................................................................ 90 9.20 e3 transmitter ..................................................................... 92 9.21 e3 trail trace buffer......................................................... 94 9.22 tributary payload processor (vtpp) .......................... 94 9.23 receive tributary path overhead processor (rtop) ........................................................................................ 96 9.24 receive tributary trace buffer (rttb)....................... 98 9.25 receive tributary bit asynchronous demapper (rtdm)........................................................................................ 99 9.26 receive tributary byte synchronous demapper . 102 9.27 ds3 mapper drop side (d3md) ......................................... 103 9.28 transmit tributary path overhead processor (ttop) ...................................................................................... 106 9.29 transmit remote alarm processor (trap).............. 107 9.30 transmit tributary bit asynchronous mapper (ttmp) ...................................................................................... 108
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential iii 9.31 transmit tributary byte synchronous mapper ... 109 9.32 ds3 mapper add side (d3ma) ............................................ 109 9.33 extract scaleable bandwidth interconnect (exsbi) ...................................................................................... 111 9.34 insert scaleable bandwidth interconnect (insbi)........................................................................................112 9.35 flexible bandwidth ports ..............................................113 9.36 jtag test access port......................................................113 9.37 microprocessor interface ...........................................115 10 normal mode register description ..................................... 138 11 test features description ...................................................... 139 11.1 jtag test port .................................................................... 142 12 operation ........................................................................................ 149 12.1 tributary indexing ............................................................ 149 12.2 clock and frame synchronization constraints .. 151 12.3 ds3 frame format.............................................................. 154 12.4 servicing interrupts....................................................... 156 12.5 using the performance monitoring features ...... 156 12.6 using the internal ds3 or e3 hdlc transmitter ... 160 12.7 using the internal ds3 or e3 data link receiver .. 164 12.8 t1/e1 loopback modes...................................................... 168 12.9 ds3 and e3 loopback modes........................................... 170 12.10 telecom bus mapper/demapper loopback modes. 173 12.11 sbi bus data formats ........................................................ 174
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential iv 12.12 jtag support ....................................................................... 196 13 functional timing......................................................................... 204 13.1 ds3 line side interface timing ...................................... 204 13.2 ds3 and e3 system side interface timing .................. 208 13.3 telecom drop bus interface timing........................... 212 13.4 telecom add bus interface timing.............................. 215 13.5 sonet/sdh serial alarm port timing .......................... 218 13.6 sbi drop bus interface timing ...................................... 219 13.7 sbi add bus interface timing ......................................... 220 14 absolute maximum ratings ....................................................... 222 15 d.c. characteristics ................................................................... 223 16 microprocessor interface timing characteristics..... 226 17 temap-84 timing characteristics ........................................... 230 18 ordering and thermal information...................................... 252 19 mechanical information............................................................ 253
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential v list of figures figure 1 - high-density line card application............................... 18 figure 2 - oc-12 multi-service switch application ...................... 19 figure 3 - fractional ds3 application .............................................. 19 figure 4 - temap-84 block diagram .................................................... 21 figure 5 - ds3/e3 framer only mode block diagram ................... 22 figure 6 - pin diagram ............................................................................. 27 figure 7 - crc multiframe alignment algorithm ......................... 70 figure 8 - jitter tolerance t1 modes............................................... 75 figure 9 - jitter tolerance e1 modes .............................................. 76 figure 10- jitter transfer t1 modes ................................................. 77 figure 11 -jitter transfer e1 modes.................................................. 78 figure 12- ds3 frame structure ....................................................... 154 figure 13- fer count vs. ber (e1 mode) ........................................... 158 figure 14- crce count vs. ber (e1 mode) ........................................ 159 figure 15- fer count vs. ber (t1 esf mode).................................... 159 figure 16- crce count vs. ber (t1 esf mode)................................. 160 figure 17- crce count vs. ber (t1 sf mode) ................................... 160 figure 18- typical data frame............................................................. 167 figure 19- example multi-packet operational sequence ........ 167 figure 20- t1/e1 line loopback............................................................ 169 figure 21- t1/e1 diagnostic digital loopback............................... 170 figure 22- ds3 diagnostic loopback diagram .............................. 171
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential vi figure 23- ds3 and e3 line loopback diagram............................... 172 figure 24- ds2 loopback diagram ..................................................... 172 figure 25- telecom diagnostic loopback diagram.................... 173 figure 26- telecom line loopback diagram .................................. 174 figure 27- boundary scan architecture....................................... 196 figure 28- tap controller finite state machine......................... 198 figure 29- input observation cell (in_cell) .................................. 201 figure 30- output cell (out_cell) .................................................... 202 figure 31- bidirectional cell (io_cell) ........................................... 202 figure 32- layout of output enable and bidirectional cells 203 figure 33- receive bipolar ds3 stream........................................... 204 figure 34- receive unipolar ds3 stream........................................ 204 figure 35- receive bipolar e3 stream ............................................. 205 figure 36- receive unipolar e3 stream .......................................... 205 figure 37- transmit bipolar ds3 stream ........................................ 206 figure 38- transmit unipolar ds3 stream ..................................... 206 figure 39- transmit bipolar e3 stream........................................... 207 figure 40- transmit unipolar e3 stream........................................ 207 figure 41- framer mode ds3 transmit input stream ................. 208 figure 42- framer mode ds3 transmit input stream with tgapclk .................................................................................... 208 figure 43- framer mode ds3 receive output stream................ 209 figure 44- framer mode ds3 receive output stream with rgapclk.................................................................................... 209
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential vii figure 45- framer mode g.751 e3 transmit input stream ......... 209 figure 46- framer mode g.751 e3 transmit input stream with tgapclk .................................................................................... 210 figure 47- framer mode g.751 e3 receive output stream........ 210 figure 48- framer mode g.751 e3 receive output stream with rgapclk.................................................................................... 210 figure 49- framer mode g.832 e3 transmit input stream ..........211 figure 50- framer mode g.832 e3 transmit input stream with tgapclk .....................................................................................211 figure 51- framer mode g.832 e3 receive output stream........ 212 figure 52- framer mode g.832 e3 receive output stream with rgapclk.................................................................................... 212 figure 53- telecom drop bus timing - sts-1 spes / au3 vcs ...... 213 figure 54- telecom drop bus timing - locked sts-1 spes / au3 vcs.............................................................................................. 214 figure 55- telecom drop bus timing - au4 vc................................. 215 figure 56- telecom add bus timing - locked sts-1 spes / au3 vcs ..................................................................................................... 216 figure 57- telecom add bus timing - locked au4 vc case......... 217 figure 58- remote serial alarm port timing ................................ 219 figure 59- sbi drop bus t1/e1 functional timing.......................... 219 figure 60- sbi drop bus ds3/e3 functional timing....................... 220 figure 61- sbi add bus justification request functional timing ........................................................................................ 220 figure 62- ds3/e3 transmit interface timing................................. 231 figure 63- ds3/e3 receive interface timing ................................... 234 figure 64- line side telecom bus input timing.............................. 237
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential viii figure 65- telecom bus output timing ............................................ 239 figure 66- telecom bus tristate output timing .......................... 239 figure 67- sbi add bus timing............................................................... 242 figure 68- sbi drop bus timing............................................................ 244 figure 69- sbi drop bus collision avoidance timing .................. 244 figure 70- egress flexible bandwidth port timing ................... 245 figure 71- ingress flexible bandwidth port timing.................. 246 figure 72- xclk input timing ................................................................ 247 figure 73- transmit line interface timing ..................................... 248 figure 74- remote serial alarm port timing ................................ 249 figure 75- jtag port interface timing ............................................ 251 figure 76- 324 pin pbga 23x23mm body............................................... 253
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential ix list of tables table 1 - e1 framer framing states ................................................ 71 table 2 - path signal label mismatch state.................................. 97 table 3 - asynchronous t1 tributary mapping ......................... 100 table 4 - asynchronous e1 tributary mapping......................... 101 table 5 - asynchronous ds3 mapping to sts-1 (stm-0/au3).... 103 table 6 - ds3 ais format...................................................................... 104 table 7 - ds3 desynchronizer clock gapping algorithm..... 106 table 8 - ds3 synchronizer bit stuffing algorithm................ 111 table 9 - register memory map........................................................115 table 10 - instruction register ....................................................... 142 table 11 - identification register ................................................... 142 table 12 - boundary scan register ................................................ 143 table 13 - indexing for 1.544 mbit/s tributaries.......................... 150 table 14 - indexing for 2.048 mbit/s tributaries.......................... 151 table 15 - 77.76 sbi and telecom bus alignment options ........ 152 table 16 - 19.44 mhz sbi to 77.76 mhz telecom to bus alignment options..................................................................................... 153 table 17 - 77.76 mhz sbi to 19.44 mhz telecom to bus alignment options..................................................................................... 153 table 18 - pmon counter saturation limits (e1 mode).............. 157 table 19 - pmon counter saturation limits (t1 mode).............. 157 table 20 - structure for carrying multiplexed links ........... 176 table 21 - t1/tvt1.5 tributary column numbering...................... 176
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential x table 22 - e1/tvt2 tributary column numbering ........................ 177 table 23 - sbi t1/e1 link rate information ..................................... 180 table 24 - sbi t1/e1 clock rate encoding....................................... 180 table 25 - ds3 link rate information............................................... 181 table 26 - ds3 clock rate encoding ................................................ 181 table 27 - t1 framing format ............................................................. 182 table 28 - t1 channel associated signaling bits........................ 183 table 29 - e1 framing format ............................................................. 185 table 30 - e1 channel associated signaling bits ....................... 186 table 31 - ds3 framing format .......................................................... 187 table 32 - ds3 block format............................................................... 188 table 33 - ds3 multi-frame stuffing format................................ 188 table 34 - e3 framing format ............................................................. 189 table 35 - e3 frame stuffing format .............................................. 190 table 36 - transparent vt1.5/tu11 format .................................... 191 table 37 - transparent vt2/tu12 format ....................................... 194 table 38 - absolute maximum ratings ............................................. 222 table 39 - d.c. characteristics......................................................... 223 table 40 - microprocessor interface read access ................ 226 table 41 - microprocessor interface write access............... 228 table 42 - rstb timing............................................................................ 230 table 43 - ds3/e3 transmit interface timing................................. 230 table 44 - ds3/e3 receive interface timing ................................... 234
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential xi table 45 - line side telecom bus input timing ? 19.44 mhz (figure 67) ................................................................................ 236 table 46 - telecom bus output timing - 19.44 mhz (figure 65 and figure 66) .................................................... 238 table 47 - telecom bus output timing ? 77.76 mhz (figure 65 and figure 66) .................................................... 238 table 48 - sbi add bus timing ? 19.44 mhz (figure 67) ................... 240 table 49 - sbi add bus timing ? 77.76 mhz (figure 67) ................... 241 table 50 - sbi drop bus timing - 19.44 mhz (figure 65 figure 68)............................................................. 242 table 51 - sbi drop bus timing - 77.76 mhz (figure 68 to figure 69)....................................................... 243 table 52 - egress flexible bandwidth port timing (figure 70) ................................................................................ 245 table 53 - ingress flexible bandwidth port timing (figure 71) ................................................................................ 246 table 54 - xclk input (figure 72)........................................................ 247 table 55 - transmit line interface timing (figure 73) ............... 248 table 56 - remote serial alarm port timing ................................ 249 table 57 - jtag port interface.......................................................... 250 table 58 - ordering information...................................................... 252 table 59 - thermal information ? theta ja vs. airflow ............ 252
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 1 1 features ? integrates three sonet/sdh vt1.5/vt2/tu11/tu12 bit asynchronous or byte synchronous mappers, three full featured m13 multiplexers with ds3 framers, three e3 framers, and three sonet/sdh ds3 mappers in a single monolithic device for terminating 84-1.544 mbit/s or 63-2.048 mbit/s data streams. ? each spe/ds3 independently programmable to allow the following modes of operation: ? five t1 modes of operation: ? three sts-1, au3 or tug3 bit asynchronous vt1.5 or tu-11 mappers with ingress or egress per tributary link monitoring. ? up to 84 t1 streams mapped as byte synchronous vt1.5 virtual tributaries into three sts-1 spes or tu-11 tributary units into three stm-1/vc3 or tug3 from a stm-1/vc4. ? ds3 m13 multiplexer with ingress or egress per link monitoring. includes the option to asynchronously map the ds3s into three sts-1/stm-0 spes. ? up to 84 ds3 multiplexed 1.544 mbit/s streams are mapped as bit asynchronous vt1.5 virtual tributaries or tu-11 tributary units, providing a transmultiplexing function between ds3 and sonet/sdh. ? up to 63 t1 streams mapped as bit asynchronous tu-12 tributary units into three stm-1/vc3 or tug3 from a stm-1/vc4. ? four e1 modes of operation: ? three sts-1, au3 or tug3 bit asynchronous vt2 or tu-12 mappers with ingress or egress per tributary link monitoring. ? up to 63 e1 streams mapped as byte synchronous vt2 virtual tributaries into three sts-1 spe or tu-12 tributary units into a stm-1/vc3 or tug3 from a stm-1/vc4. ? up to 63 2.048 mbit/s streams multiplexed into three ds3s following the itu-t g.747 recommendation. includes the option to asynchronously map the ds3s into three sts-1/stm-0 spes.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 2 ? up to 63 ds3 multiplexed 2.048 mbit/s streams are mapped as bit asynchronous vt2 virtual tributaries or tu-12 tributary units, providing a transmultiplexing function between ds3 and sonet/sdh. ? two unchannelized ds3 modes of operation: ? standalone unchannelized ds3 framer mode for access to the entire ds3 payload. ? up to three ds3 streams are mapped bit asynchronously into vc-3s. ? standalone unchannelized e3 framer mode (itu-t rec. g.751 or g.832) for access to the entire e3 payload. ? up to 84 vt1.5/tu11 or 63 vt2/tu12 tributaries can be passed between the line sonet/sdh bus and the sbi bus as transparent virtual tributaries with pointer processing. ? supports a byte serial scaleable bandwidth interconnect (sbi) bus interface for high density system side device interconnection of up to 84 t1 streams, 63 e1 streams, 3 ds3 streams or 3 e3 streams. this interface also supports transparent virtual tributaries when used with the sonet/sdh mapper. ? supports insertion and extraction of arbitrary rate (eg. fractional ds3) data streams to and from the sbi bus interface. ? provides jitter attenuation in the t1 or e1 receive and transmit directions. ? provides three independent de-jittered 1.544 mhz or 2.048 mhz recovered clocks for system timing and redundancy. ? provides per link diagnostic and line loopbacks. ? provides an on-board programmable binary sequence generator and detector for error testing at ds3 and e3 rates. includes support for patterns recommended in itu-t o.151. ? also provides prbs generators and detectors on each tributary for error testing at 1.544 mbit/s and 2.048 mbit/s rates as recommended in itu-t o.151 and o.152. ? supports the m23 and c-bit parity ds3 formats.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 3 ? when configured to operate as a ds3 or e3 framer, gapped transmit and receive clocks can be optionally generated for interface to link layer devices which only need access to payload data bits. ? ds3 or e3 transmit clock source can be selected from either an external oscillator or from the receive side clock (loop-timed). ? provides a sonet/sdh add/drop bus interface with integrated vt1.5, tu-11, vt2 and tu-12 mapper for t1and e1 streams. also provides a ds3 mapper. ? system side interface is an sbi bus. ? provides a generic 8-bit microprocessor bus interface for configuration, control and status monitoring. ? provides a standard 5 signal p1149.1 jtag test port for boundary scan board test purposes. ? low power 1.8v/3.3v cmos technology. all pins are 5v tolerant. ? 324-pin fine pitch pbga package (23mm x 23mm). supports industrial temperature range (-40 o c to 85 o c) operation. each one of 84 t1 performance monitor sections: ? provides non-intrusive performance monitoring of either ingress or egress paths, as selected on a per-tributary basis. ? frames to ds-1 signals in sf, slc ? 96 and esf formats. ? frames to ttc jt-g.704 multiframe formatted j1 signals. supports the alternate crc-6 calculation for japanese applications. ? provides red, yellow, and ais alarm integration. ? supports rai-ci and ais-ci alarm detection and generation. ? non-intrusive performance monitoring provided by the temap-84 also provides an hdlc interface with 128 bytes of buffering for terminating the facility data link in either the ingress or egress paths, as selected on a per- tributary basis. ? provides inband loopback code detection.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 4 ? provides performance monitoring counters sufficiently large as to allow performance monitor counter polling at a minimum rate of once per second. optionally, updates the performance monitoring counters and interrupts the microprocessor once per second. ? an unframed pseudo-random sequence user selectable from 2 7 ?1, 2 11 ?1, 2 15 ? 1 or 2 20 ?1, may be detected in the t1 stream in either the ingress or egress directions. the detector counts pattern errors using a 16-bit non-saturating prbs error counter. ? line side interface is either from the ds3 interface via the m13 multiplex or from the sonet/sdh drop bus via the vt1.5, tu-11, vt2 or tu-12 demapper. ? frames in the presence of and detects the ?japanese yellow? alarm. each one of 63 e1 performance monitor sections: ? provides non-intrusive performance monitoring of either ingress or egress paths, as selected on a per-tributary basis. ? frames to itu-t g.704 basic and crc-4 multiframe formatted e1 signals. the framing procedures are consistent itu-t g.706 specifications. ? non-intrusive performance monitoring provided by the temap-84 also provides an hdlc interface with 128 bytes of buffering for terminating the facility data link in either the ingress or egress paths, as selected on a per- tributary basis. ? provides performance monitoring counters sufficiently large as to allow performance monitor counter polling at a minimum rate of once per second. optionally, updates the performance monitoring counters and interrupts the microprocessor once per second. ? an unframed pseudo-random sequence user selectable from 2 7 ?1, 2 11 ?1, 2 15 ? 1 or 2 20 ?1, may be detected in the e1 stream in either the ingress or egress directions. the detector counts pattern errors using a 16-bit non-saturating prbs error counter. each one of 84 transmit tributaries: ? may be timed to its associated receive clock (loop timing) or may derive its timing from a common egress clock or a common transmit clock; the transmit line clock may be synthesized from an n*8 khz reference. ? provides a digital phase locked loop for generation of a low jitter transmit clock.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 5 ? provides a fifo buffer for jitter attenuation in the transmitter. each one of three sonet/sdh tributary path processing sections: ? interfaces with a byte wide telecom add/drop bus, interfacing directly with the pm5362 tupp-plus and pm5342 spectra-155 at 19.44 mhz. ? seamlessly interfaces with a 77.76 mhz drop bus. interfaces to a 77.76 mhz add bus with minimal external logic. ? compensates for pleisiochronous relationships between incoming and outgoing higher level (sts-1, au4, au3) synchronous payload envelope frame rates through processing of the lower level tributary pointers. ? optionally frames to the h4 byte in the path overhead to determine tributary multi-frame boundaries and generates change of loss-of-frame status interrupts. ? detects loss of pointer (lop) and re-acquisition for each tributary and optionally generates interrupts. ? detects tributary path alarm indication signal (ais) and return to normal state for each tributary and optionally generates interrupts ? detects tributary elastic store underflow and overflow and optionally generates interrupts. ? provides individual tributary path signal label register that hold the expected label and detects tributary path signal label mismatch alarms (pslm) and return to matched state for each tributary and optionally generates interrupts. ? detects tributary path signal label unstable alarms (pslu) and return to stable state for each tributary and optionally generates interrupts. ? detects assertion and removal of tributary extended remote defect indications (rdi) for each tributary and optionally generates interrupts. ? calculates and compares the tributary path bip-2 error detection code for each tributary and configurable to accumulate the bip-2 errors on block or bit basis in internal registers. ? allows insertion of all-zeros or all-ones tributary idle code with unequipped indication and valid pointer into any tributary under software control. ? allows software to force the ais insertion on a per tributary basis.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 6 ? inserts valid h4 byte and all-zeros fixed stuff bytes. remaining path overhead bytes (j1, b3, c2,g1, f2, z3, z4, z5) are set to all-zeros. ? inserts valid pointers and all-zeros transport overhead bytes on the outgoing telecom add bus, with valid control signals. ? support in-band error reporting by updating the febe, rdi and auxiliary rdi bits in the v5 byte with the status of the incoming stream and remote alarm pins. ? calculates and inserts the tributary path bip-2 error detection code for each tributary. each one of three sonet/sdh vt/tu mapper sections: ? inserts up to 28 bit asynchronous mapped vt1.5 virtual tributaries into an sts-1 spe from t1 streams. ? inserts up to 28 bit asynchronous mapped tu-11 tributary units into a stm- 1/vc4 tug3 or stm-1/vc3 from t1 streams. ? inserts up to 28 byte synchronous mapped vt1.5 virtual tributaries into an sts-1 spe or tu-11 tributary units into an stm-1/vc3 or tug3 from a stm-1/vc4. ? inserts up to 21 bit asynchronous mapped vt2 virtual tributaries into an sts-1 spe from e1 streams. ? inserts up to 21 bit asynchronous mapped tu-12 tributary units into an stm- 1/vc4 tug3 or stm-1/vc3 from e1 or t1 streams. ? processes the tributary trace message (j2) of the tributaries carried in each sts-1/tug-3 synchronous payload envelope. ? bit asynchronous mapping assigns stuff control bits for all streams independently using an all digital control loop. stuff control bits are dithered to produce fractional mapping jitter at the receiving desynchronizer. ? sets all fixed stuff bits for asynchronous mappings to zeros or ones per microprocessor control ? extracts up to 28 bit asynchronous mapped vt1.5 virtual tributaries from an sts-1 spe into t1 streams via an optional elastic store. ? extracts up to 28 bit asynchronous mapped tu-11 tributary units from an stm- 1/vc4 tug3 or stm-1/vc3 into t1 streams via an optional elastic store.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 7 ? extracts up to 21 bit asynchronous mapped vt2 virtual tributaries from an sts-1 spe into e1 streams via an optional elastic store. ? extracts up to 21 bit asynchronous mapped tu-12 tributary units from an stm- 1/vc4 tug3 or stm-1/vc3 into e1 or t1 streams via an optional elastic store. ? demapper ignores all transport overhead bytes, path overhead bytes and stuff (r) bits ? performs majority vote c-bit decoding to detect stuff requests. each one of three sonet/sdh ds3 mapper sections: ? maps a ds3 stream into an sts-1 spe (au3). ? sets all fixed stuff (r) bits to zeros or ones per microprocessor control ? extracts a ds3 stream from an sts-1 spe (au3). ? demapper ignores all transport overhead bytes, path overhead bytes and stuff (r) bits ? performs majority vote c-bit decoding to detect stuff requests ? complies with ds3 to sts-1 asynchronous mapping standards each one of three ds3 receiver sections: ? frames to a ds3 signal with a maximum average reframe time of less than 1.5 ms (as required by tr-tsy-000009 section 4.1.2 and tr-tsy-000191 section 5.2). ? decodes a b3zs-encoded signal and indicates line code violations. the definition of line code violation is software selectable. ? provides indication of m-frame boundaries from which m-subframe boundaries and overhead bit positions in the ds3 stream can be determined by external processing. ? detects the ds3 alarm indication signal (ais) and idle signal. detection algorithms operate correctly in the presence of a 10 -3 bit error rate. ? detection times of 2.23 ms and 13.5 ms are supported. the fast detection time meets the requirement of tr-tsy-000191 section 5. the longer detection time
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 8 meets the ansi t1m1.3 section 7.1.2.4 requirement that ais be detected in less than 100 ms and is intended for non-boc (bell operating company) applications. ? extracts valid x-bits and indicates far end receive failure (ferf). the far end receive failure status only changes if the two x-bits are the same. the status is buffered for two m-frames, ensuring a better than 99.99% chance of freezing the correct status for the duration of the out of frame occurrence. ? accumulates up to 65,535 line code violation (lcv) events per second, 65,535 p-bit parity error events per second, 1023 f-bit or m-bit (framing bit) events per second, 65,535 excessive zero (exz) events per second, and when enabled for c-bit parity mode operation, up to 16,383 c-bit parity error events per second, and 16,383 far end block error (febe) events per second (note that, over a one second interval, only 9399 p-bit errors, c-bit parity errors, or febe events can occur). ? detects and validates bit-oriented codes in the c-bit parity far end alarm and control channel. ? terminates the c-bit parity path maintenance data link with an integral hdlc receiver having a 128-byte deep fifo buffer with programmable interrupt threshold. supports polled or interrupt-driven operation. selectable none, one or two address match detection on first byte of received packet. ? programmable pseudo-random test-sequence detection?(up to 2 32 -1 bit length patterns conforming to itu-t o.151 standards) and analysis features. each one of three ds3 transmit sections: ? provides the overhead bit insertion for a ds3 stream. ? provides a bit serial clock and data interface, and allows the m-frame boundary and/or the overhead bit positions to be located via an external interface ? provides b3zs encoding. ? generates an b3zs encoded 100? repeating pattern to aid in pulse mask testing. ? inserts far end receive failure (ferf), the ds3 alarm indication signal (ais) and the idle signal when enabled by internal register bits.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 9 ? provides optional automatic insertion of far end receive failure (ferf) on detection of loss of signal (los), out of frame (oof), alarm indication signal (ais) or red alarm condition. ? provides diagnostic features to allow the generation of line code violation error events, parity error events, framing bit error events, and when enabled for the c- bit parity application, c-bit parity error events, and far end block error (febe) events. ? supports insertion of bit-oriented codes in the c-bit parity far end alarm and control channel. ? optionally inserts the c-bit parity path maintenance data link with an integral hdlc transmitter. supports polled and interrupt-driven operation. ? provides programmable pseudo-random test sequence generation (up to 2 32 -1 bit length sequences conforming to itu-t o.151 standards) or any repeating pattern up to 32 bits. the test pattern can be framed or unframed. diagnostic abilities include single bit error insertion or error insertion at bit error rates ranging from 10 -1 to 10 -7 . m23 multiplexer section: ? multiplexes 7 ds2 bit streams into a single m23 format ds3 bit stream. ? performs required bit stuffing/destuffing including generation and interpretation of c-bits. ? includes required fifo buffers for rate adaptation in the multiplex path. ? allows insertion and detection of per ds2 payload loopback requests encoded in the c-bits to be activated under microprocessor control. ? internally generates a ds2 clock for use in integrated m13 or c-bit parity multiplex applications. alternatively accepts external ds2 clock reference. ? allows per ds2 alarm indication signal (ais) to be activated or cleared for either direction under microprocessor control. ? allows ds2 alarm indication signal (ais) to be activated or cleared in the demultiplex direction automatically upon loss of ds3 frame alignment or signal. ? supports c-bit parity ds3 format.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 10 ds2 framer section: ? frames to a ds2 (ansi t1.107 section 8) signal with a maximum average reframe time of less than 7 ms (as required by tr-tsy-000009 section 4.1.2 and tr-tsy-000191 section 5.2). ? detects the ds2 alarm indication signal (ais) in 9.9 ms in the presence of a 10 -3 bit error rate. ? extracts the ds2 x-bit remote alarm indication (rai) bit and indicates far end receive failure (ferf). the far end receive failure status only changes when the associated bit has been in the same state for two consecutive frames. the status is buffered for six m-frames, ensuring a better than 99.9% chance of freezing the correct status for the duration of the out of frame occurrence. ? accumulates up to 255 ds2 m-bit or f-bit error events per second. ds2 transmitter section: ? generates the required x, f, and m bits into the transmitted ds2 bit stream. allows inversion of inserted f or m bits for diagnostic purposes. ? provides for transmission of far end receive failure (ferf) and alarm indication signal (ais) under microprocessor control. ? provides optional automatic insertion of far end receive failure (ferf) on detection of out of frame (oof), alarm indication signal (ais) or red alarm condition. m12 multiplexer section: ? multiplexes four ds1 or three 2048 kbit/s (according to itu-t rec. g.747) bit streams into a single m12 format ds2 bit stream. ? performs required bit stuffing including generation and interpretation of c-bits. ? includes required fifo buffers for rate adaptation in the multiplex path. ? performs required inversion of second and fourth multiplexed ds1 streams as required by ansi t1.107 section 7.2. ? allows insertion and detection of per ds1 payload loopback requests encoded in the c-bits to be activated under microprocessor control.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 11 ? allows per tributary alarm indication signal (ais) to be activated or cleared for either direction under microprocessor control. ? allows automatic tributary ais to be activated upon ds2 out of frame. each one of three e3 framer sections: ? frames to g.751 and g.832 e3 unchannelized data streams. ? for g.832, terminates the trail trace and either the network requirement or the general purpose data link. each one of three e3 transmit sections: ? provides frame insertion for the g.751 or g.832 e3 applications, alarm insertion, and diagnostic features. ? for g.832, the trail trace is inserted, and an integral hdlc transmitter is provided to insert either the network requirement or the general purpose data link. scaleable bandwidth interconnect (sbi) bus: ? provides a high density byte serial interconnect for all framed and unframed temap-84 links. utilizes an add/drop configuration to asynchronously mutliplex up to 84 t1s, 63 e1s, 3 e3s or 3 ds3s, with multiple payload or link layer processors. ? operates at either 19.44 mhz or 77.76 mhz. ? external devices can access unframed ds3, framed unchannelized ds3, unframed e3, framed unchannelized e3, unframed (clear channel) t1s, framed t1s (byte synchronous mapping only), unframed (clear channel) e1s, framed e1s (byte synchronous mapping only), arbitrary rate clear channel data stream (eg. fractional ds3), transparent virtual tributaries or transparent tributary units over this interface. ? up to three arbitrary rate data streams inserted into and extracted from the sbi via bit serial ports. ? transparent vt/tu access can be selected only when tributaries are mapped into sonet/sdh.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 12 ? transmit timing is mastered either by the temap-84 or a layer 2 device connecting to the sbi bus. timing mastership is selectable on a per tributary basis, where a tributary is either an individual t1, e1, e3 or a ds3.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 13 2 applications ? sonet/sdh add drop multiplexers ? sonet/sdh terminal multiplexers ? m23 based m13 multiplexer ? c-bit parity based m13 multiplexer ? channelized and unchannelized ds3 frame relay interfaces ? optical access equipment
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 14 3 references ? american national standard for telecommunications - digital hierarchy - synchronous ds3 format specifications, ansi t1.103-1993 ? american national standard for telecommunications ? ansi t1.105 ? ?synchronous optical network (sonet) ? basic description including multiplex structure, rates, and formats,? october 27, 1995. ? american national standard for telecommunications ? ansi t1.105.02 ? ?synchronous optical network (sonet) ? payload mappings,? october 27, 1995. ? american national standard for telecommunications - digital hierarchy - formats specification, ansi t1.107-1995 ? american national standard for telecommunications - digital hierarchy - layer 1 in-service digital transmission performance monitoring, ansi t1.231-1997 ? american national standard for telecommunications - carrier to customer installation - ds-1 metallic interface specification, ansi t1.403-1995 ? american national standard for telecommunications - customer installation?to- network - ds3 metallic interface specification, ansi t1.404-1994 ? american national standard for telecommunications - integrated services digital network (isdn) primary rate- customer installation metallic interfaces layer 1 specification, ansi t1.408-1990 ? bell communications research, tr?tsy-000009 - asynchronous digital multiplexes requirements and objectives, issue 1, may 1986 ? bell communications research - ds-1 rate digital service monitoring unit functional specification, ta-tsy-000147, issue 1, october, 1987 ? bell communications research - alarm indication signal requirements and objectives, tr-tsy-000191 issue 1, may 1986 ? bell communications research - wideband and broadband digital cross- connect systems generic criteria, tr-nwt-000233, issue 3, november 1993
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 15 ? bell communications research ? digital interface between the slc ? 96 digital loop carrier system and a local digital switch, tr-tsy-000008, issue 2, august 1987 ? bellcore gr-253-core ? ?sonet transport systems: common criteria,? issue 2, revision 1, december 1997. ? bell communications research - integrated digital loop carrier generic requirements, objectives, and interface, tr-nwt-000303, issue 2, december, 1992 ? bell communications research - transport systems generic requirements (tsgr): common requirement, tr-tsy-000499, issue 5, december, 1993 ? bell communications research - otgr: network maintenance transport surveillance - generic digital transmission surveillance, tr-tsy-000820, section 5.1, issue 1, june 1990 ? at&t - requirements for interfacing digital terminal equipment to services employing the extended superframe format, tr 54016, september, 1989. ? at&t - accunet t1.5 - service description and interface specification, tr 62411, december, 1990 ? itu study group xviii ? report r 105, geneva, 9-19 june 1992 ? etsi - ets 300 011 - isdn primary rate user-network interface specification and test principles, 1992. ? etsi - ets 300 233 - access digital section for isdn primary rates, may 1994 ? etsi - ets 300 324-1 - signaling protocols and switching (sps); v interfaces at the digital local exchange (le) v5.1 interface for the support of access network (an) part 1: v5.1 interface specification, february, 1994. ? etsi - ets 300 347-1 - signaling protocols and switching (sps); v interfaces at the digital local exchange (le) v5.2 interface for the support of access network (an) part 1: v5.2 interface specification, september 1994. ? etsi ets 300 417-1-1 ? ?transmission and multiplexing (tm); generic functional requirements for synchronous digital hierarchy (sdh) equipment; part 1-1: generic processes and performance,? january, 1996. ? etsi, generic functional requirements for synchronous digital hierarchy (sdh) equipment, jan 1996
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 16 ? itu-t - recommendation g.704 - synchronous frame structures used at primary hierarchical levels, july 1995. ? itu-t - recommendation g.706 - frame alignment and crc procedures relating to g.704 frame structures, 1991. ? itu-t recommendation g.707 ? network node interface for the synchronous digital hierarchy, 1996 ? itu-t recommendation g.747 ? second order digital multiplex equipment operating at 6312 kbit/s and multiplexing three tributaries at 2048 kbit/s, 1988 ? itu-t recommendation g.751, - ccitt blue book fasc. iii.4, "digital multiplex equipments operating at the third order bit rate of 34,368 kbit/s and the fourth order bit rate of 139,264 kbit/s and using positive justification?, 1988 ? itu-t recommendation g.775, - loss of signal (los) and alarm indication signal (ais) defect detection and clearance criteria, 11/94 ? itu-t recommendation g.783 ? characteristics of synchronous digital hierarchy (sdh) equipment functional blocks, april, 1997. ? itu-t recommendation g.823, - the control of jitter and wander within digital networks which are based on the 2048 kbit/s hierarchy, 03/94 ? itu-t recommendation g.832 - "transport of sdh elements on pdh networks: frame and multiplexing structures", 1993. ? itu-t recommendation g.964, - v-interfaces at the digital local ex?hange (le) - v5.1 interface (based on 2048 kbit/s) for the support of access network (an), june 1994. ? itu-t recommendation g.965, - v-interfaces at the digital local ex?hange (le) - v5.2 interface (based on 2048 kbit/s) for the support of access network (an), march ?995. ? itu-t - recommendation i.431 - primary rate user-network interface ? layer 1 specification, 1993. ? itu-t recommendation o.151 ? error performance measuring equipment operating at the primary rate and above, october 1992 ? itu-t recommendation o.152 ? error performance measuring equipment for bit rates of 64 kbit/s and n x 64 kbit/s, october 1992
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 17 ? itu-t recommendation o.153 - basic parameters for the measurement of error performance at bit rates below the primary rate, october 1992. ? itu-t recommendation q.921 - isdn user-network interface data link layer specification, march 1993 ? international organization for standardization, iso 3309:1984 - high-level data link control procedures - frame structure ? ttc standard jt-g704 - frame structures on primary and secondary hierarchical digital interfaces, 1995. ? ttc standard jt-g706 - frame synchronization and crc procedure ? ttc standard jt-i431 - isdn primary rate user-network interface layer 1 - specification, 1995. ? nippon telegraph and telephone corporation - technical reference for high- speed digital leased circuit services, third edition, 1990.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 18 4 application examples PM5366 temap-84 in conjunction with pmc's pm4318 octliu provides a high- density line card for sonet/sdh add/drop multiplexers' as shown in figure 1. figure 1 - high-density line card application oc-12 pm5313 spectra-6 22 pm5363 tupp-622 eas t car d tributary cross-connect oc-12 pm5313 spectra-6 22 pm5363 tupp-622 west card PM5366 temap-84 pm4318 octliu pm4318 octliu pm4318 octliu 8 x t1 or 8 x e1 sbi work prot prot dr op add figure 2 shows a oc-12 multi-service switch application, whereby PM5366 temap-84 provides vt/tu mapping and performance monitoring. PM5366 temap-84 connects seamlessly to pmc's link layer products using the scaleable bandwidth interconnect (sbi) bus.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 19 figure 2 - oc-12 multi-service switch application oc-12 pm5313 spectra-622 PM5366 temap-84 PM5366 temap-84 PM5366 temap-84 PM5366 temap-84 pm7384 freedm-8 4 pm73122 aal1gator -32 packet/cell internetworking function appi utopia pm7324 s/uni-atlas pm7826 s/uni-apex utopia sbi appi ds3 liu ds3 liu ds3 liu telecom figure 3 - fractional ds3 application PM5366 temap-84 sbi bus ds3 liu fpga fpga i f b w c l k i f b w e n i f b w d a t r s c l k t i c l k r d a t o r m f p o e f b w c l k e f b w e n e f b w d a t e f b w d r e q 44.736 mhz t m f p o t d a t i to support evolving fractional ds3 applications, flow-controlled ports provide access to sbi bus bandwidth. several non-standard schemes have been
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 20 devised to use a portion of the ds3 payload. given that these protocols are subject to change, they are best supported by external programmable logic. figure 3 illustrates one implementation. other implementations and applications are possible. in the ingress direction, the framed ds3 is presented to an fpga, whose responsibility it is to identify the utilitized bits of the payload. valid bits are indicated to the ingress flexible bandwidth port via an enable signal, ifbwen. the bits are collected into bytes by the temap-84 and inserted into the payload of the sbi drop bus. in the egress direction, an fpga formats the payload of a ds3, while the temap-84 inserts the ds3 frame overhead. the fpga contains a data buffer. based on the ds3 frame alignment dictated by the tmfpo signal, the fpga inserts bits from the data buffer into the ds3 payload according to the protocol supported. to ensure the data buffer is replenished, the fpga asserts the efbwdreq signal to initiate the transfer of a bit. the egress flexible bandwidth port responds by asserting efwben coincident with efwbdat presenting valid data. the sbi add bus participates by modulating its sajust_req output to match the sbi data rate to that required to keep internal fifos centered.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 21 5 block diagram 5.1 top level block diagram figure 4 shows the complete temap-84. t1 links can be multiplexed into the ds3s or can be mapped into the telecom bus as sonet vt1.5 virtual tributaries or as sdh tu-11 or tu-12 tributary units. e1 links can be mapped into the telecom bus as sonet vt2 virtual tributaries or as sdh tu-12 tributary units. system side access to the t1s and e1s is available through the sbi bus. ds3 line side access is via the clock and data interface for line interface units (lius) or ds3 mapped into the sonet/sdh telecom bus. unchannelized ds3 system side access is available through the sbi bus. figure 4 - temap-84 block diagram t1/e1 jat84 ttmp (bit) rtdm (bit) m13 m13 m13 m13 m13 m13 m13 m13 ds3/e3 frmr m13 m13 ds3/e3 tran trap m13 m13 vtpp m13 m13 vtpp m13 m13 sipo m13 m13 piso m13 m13 d3ma m13 m13 d3md telecom bus telecom bus lius lius sbi 155 ttop m13 m13 rtop/ rttb t1/e1 jat84 exsbi insbi insbi (byte) exsbi (byte) egress flexible b/w port ingress flexible b/w port ds3/e3 tx system i/f ds3/e3 rx system i/f transmux datapath t1/e1 frmr84
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 22 5.2 ds3/e3 framer only block diagram figure 5 shows the temap-84 configured as a ds3 or e3 framer. in this mode the temap-84 provides access up to three full ds3/e3 unchannelized payloads. the payload access (right side of diagram) has two clock and data interfacing modes, one utilizing a gapped clock to mask out the ds3/e3 overhead bits and the second utilizing an ungapped clock with overhead indications on a separate overhead signal. the sbi bus can also be used to provide access to the unchannelized ds3/e3. figure 5 - ds3/e3 framer only mode block diagram tclk tpos/tdat tneg/tmfp rclk/vclk rpos/rdat rneg/rlcv tdati tfpi/tmfpi rdato rfpo/rmfpo rovrhd tran ds3/e3 transmit framer frmr ds3/e3 receive framer b3zs/ hdb3 encode b3zs/ hdb3 decode pmon perf. monitor rdlc rx hdlc tdpr tx hdlc tfpo/tmfpo/tgapclk rgapclk/rsclk ticlk 3x
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 23 6 description the PM5366 high density 84/63 channel vt/tu mapper and m13 multiplexer (temap-84) is a feature-rich device for use in any applications requiring high density link termination over t1 and e1 (g.747) channelized ds3 or t1 and e1 channelized sonet/sdh facilities. the temap-84 supports asynchronous multiplexing and demultiplexing of 84 1.544 mbit/s or 63 2.048 mbit/s tributaries into three ds3 signals as specified by ansi t1.107, bell communications research tr-tsy-000009 and itu-t rec. g.747. it supports bit asynchronous or byte synchronous mapping and demapping of 84 t1s or 63 e1s into sonet/sdh as specified by ansi t1.105, bell communications research gr-253-core and itu-t recommendation g.707. the temap-84 also supports mapping of 63 t1s into sdh via tu-12s. up to 84 transparent vt1.5s and tu-11s or 63 transparent vt2s and tu-12s can be transferred between the sonet/sdh interface and the sbi bus interface. this device can also be configured as a ds3 or e3 framer, providing external access to the full ds3 or e3 payload, or a vt/tu mapper, providing access to unframed 1.544 mbit/s and 2.048 mbit/s links. the temap-84 can be used as a sonet/sdh vt/tu mapper or m13 multiplexer with performance monitoring in either the ingress or egress direction for up to 84 t1s or 63 e1s. each of the t1 and e1 jitter attenuators and performance monitors is independently software configurable, allowing timing master and feature selection without changes to external wiring. 1.544 mbit/s and 63 2.048 mbit/s tributaries may be mixed at a vc-3/tug-3/ds3 granularity. in the ingress direction, each of the 84 t1 links is either demultiplexed from a channelized ds3 or extracted from sonet vt1.5, tu-11 or tu-12 mapped bus. each t1 performance monitor can be configured to frame to the common ds1 signal formats (sf, slc ? 96, esf). t1 performance monitoring with accumulation of crc-6 errors, framing bit errors, out-of-frame events, and changes of frame alignment is provided. . the temap-84 also detects the presence of esf bit oriented codes, and detects and terminates hdlc messages on the esf data link. the hdlc messages are terminated in a 128 byte fifo.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 24 in the ingress direction, each of the 63 2.048 mbit/s links is either demultiplexed from a ds3 according to itu-t rec. g.747 or extracted from sonet/sdh vt2 or tu-12 mapped bus. the e1 performance monitors support detection of various alarm conditions such as loss of frame, loss of signaling multiframe and loss of crc multiframe. the e1 framers also support reception of remote alarm signal, remote multiframe alarm signal, alarm indication signal, and time slot 16 alarm indication signal. e1 performance monitoring with accumulation of crc-4 errors, far end block errors and framing bit errors is provided. the temap-84 provides a receive hdlc controller for the detection and termination of messages on the national use bits. the temap-84 can generate a low jitter transmit clock from a variety of clock references, and also provides jitter attenuation in the receive path. three jitter attenuated recovered t1/e1 clocks can be routed outside the temap-84 for network timing applications. a scaleable bandwidth interconnect (sbi) high density byte serial system interface provides higher levels of integration and dense interconnect. the sbi bus interconnects up to 84 t1s or 63 e1 both synchronously or asynchronously. the sbi allows transmit timing to be mastered by either the temap-84 or link layer device connected to the sbi bus. in addition to unframed t1s and e1s, the temap-84 can transport framed or unframed ds3 or e3 links over the sbi bus. when configured as a ds3 multiplexer/demultiplexer or ds3 framer, the temap- 84 accepts and outputs either digital b3zs-encoded bipolar or unipolar signals compatible with m23 and c-bit parity applications. in the ds3 receive direction, the temap-84 frames to ds3 signals with a maximum average reframe time of 1.5 ms in the presence of 10 -3 bit error rate and detects line code violations, loss of signal, framing bit errors, parity errors, c- bit parity errors, far end block errors, ais, far end receive failure and idle code. the ds3 framer is an off-line framer, indicating both out of frame (oof) and change of frame alignment (cofa) events. the error events (c-bit, febe, etc.) are still indicated while the framer is oof, based on the previous frame alignment. when in c-bit parity mode, the path maintenance data link and the far end alarm and control (feac) channels are extracted. hdlc receivers are provided for path maintenance data link support. in addition, valid bit-oriented codes in the feac channels are detected and are available through the microprocessor port. ds3 error event accumulation is also provided by the temap-84. framing bit errors, line code violations, excessive zeros occurrences, parity errors, c-bit
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 25 parity errors, and far end block errors are accumulated. error accumulation continues even while the off-line framers are indicating oof. the counters are intended to be polled once per second, and are sized so as not to saturate at a 10 -3 bit error rate. transfer of count values to holding registers is initiated through the microprocessor interface. in the ds3 transmit direction, the temap-84 inserts ds3 framing, x and p bits. when enabled for c-bit parity operation, bit-oriented code transmitters and hdlc transmitters are provided for insertion of the feac channels and the path maintenance data links into the appropriate overhead bits. alarm indication signals, far end receive failure and idle signal can be inserted using either internal registers or can be configured for automatic insertion upon received errors. when m23 operation is selected, the c-bit parity id bit (the first c-bit of the first m sub-frame) is forced to toggle so that downstream equipment will not confuse an m23-formatted stream with stuck-at-1 c-bits for c-bit parity application. transmit timing is from an external reference or from the receive direction clock. the temap-84 also supports diagnostic options which allow it to insert, when appropriate for the transmit framing format, parity or path parity errors, f-bit framing errors, m-bit framing errors, invalid x or p-bits, line code violations, all-zeros, ais, remote alarm indications, and remote end alarms. a pseudo random binary sequence (prbs) can be inserted into a ds3 payload and checked in the receive ds3 payload for bit errors. a fixed 100100? pattern is available for insertion directly into the b3zs encoder for proper pulse mask shape verification. the temap-84 may be used as an e3 framer for the transport of framed but unchannelized e3 data streams complying to the itu-t recommendations g.751 or g.832. the line interface may be configured as either unipolar or hdb3-encoded. when configured in ds3 multiplexer mode, seven 6312 kbit/s data streams are demultiplexed and multiplexed into and out of each ds3 signal. bit stuffing and rate adaptation is performed. the c-bits are set appropriately, with the option of inserting ds2 loopback requests. interrupts can be generated upon detection of loopback requests in the received ds3. ais may be inserted in the any of the 6312 kbit/s tributaries in both the multiplex and demultiplex directions. c-bit parity is supported by sourcing a 6.3062723 mhz clock, which corresponds to a stuffing ratio of 100%. framing to the demultiplexed 6312 kbit/s data streams supports ds2 (ansi ti.107) frame formats. the maximum average reframe time is 7ms for ds2. far end receive failure is detected and m-bit and f-bit errors are accumulated. the ds2 framer is an off-line framer, indicating both oof and cofa events. error
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 26 events (ferf, merr, ferr, perr, rai, framing word errors) are still indicated while the ds2 framer is indicating oof, based on the previous alignment. each of the seven 6312 kbit/s multiplexers per ds3 may be independently configured to multiplex and demultiplex four 1544 kbit/s ds1s or three 2048 kbit/s according to itu-t rec. g.747 into and out of a ds2 formatted signal. tributary frequency deviations are accommodated using internal fifos and bit stuffing. the c-bits are set appropriately, with the option of inserting ds1 loopback requests. interrupts can be generated upon detection of loopback requests in the received ds2. ais may be inserted in any of the low speed tributaries in both multiplex and demultiplex directions. when configured as a ds3 or e3 framer the unchannelized payload of the ds3 and e3 links are available to an external device. the sonet/sdh line side interface provides sts-1 spe synchronous payload envelope processing and generation, tug3 tributary unit group processing and generation within a vc4 virtual container and vc3 virtual container processing and generation. the payload processor aligns and monitors the performance of sonet virtual tributaries (vts) or sdh tributary units (tus). maintenance functions per tributary include detection of loss of pointer, ais alarm, tributary path signal label mismatch and tributary path signal label unstable alarms. optionally interrupts can be generated due to the assertion and removal of any of the above alarms. counts are accumulated for tributary path bip-2 errors on a block or bit basis and for febe indications. the synchronous payload envelope generator generates all tributary pointers and calculates and inserts tributary path bip-2. the generator also inserts febe, rdi and enhanced rdi in the v5 byte. software can force ais insertion on a per tributary basis. a sonet/sdh mapper maps and demaps up to 84 t1s, 63 e1s or three ds3s into three sts-1 spes, tug3s or vc3s through three elastic stores. the fixed stuff (r) bits are all set to zeros or ones under microprocessor control. the bit asynchronous demapper performs majority vote c-bit decoding to detect stuff requests for t1, e1 and ds3 asynchronous mappings. the vt1.5/vt2/tu- 11/tu-12 mapper uses an elastic store and a jitter attenuator capability to minimize jitter introduced via bit stuffing. the temap-84 is configured, controlled and monitored via a generic 8-bit microprocessor bus through which all internal registers are accessed. all sources of interrupts can be masked and acknowledged through the microprocessor interface.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 27 7 pin diagram the temap-84 is packaged in a 324-pin pbga package having a body size of 23mm by 23mm and a ball pitch of 1.0 mm. the center 36 balls are not used as signal i/os and are thermal balls. pin names and locations are defined in the pin description table in section 8. mechanical information for this package is in the section 19. figure 6 - pin diagram 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a b c d e f g h 324 pbga j vss vss vss vss vss vss k vss vss vss vss vss vss l vss vss vss vss vss vss m vss vss vss vss vss vss n vss vss vss vss vss vss p vss vss vss vss vss vss r t bottom view u v w y aa a b 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 28 8 pin description pin name type pin no. function ds3 and e3 line side interface rclk[3] rclk[2] rclk[1] input p1 t1 y1 receive input clocks (rclk[3:1]). rclk[3:1] provide the receive direction timing for the three ds3s or e3s. rclk[3:1] are nominally 44.736 mhz or 34.368 mhz, 50% duty cycle clock inputs. rpos/rdat[3] rpos/rdat[2] rpos/rdat[1] input p2 u1 v3 positive input pulse (rpos[3:1]). rpos[3:1] represent the positive pulses received on the b3zs- encoded ds3s or hdb3-encoded e3s when dual rail input format is selected. receive data input (rdat[3:1]). rdat[3:1] represent the nrz (unipolar) ds3 or e3 input data streams when single rail input format is selected. rpos[3:1] and rdat[3:1] are sampled on the rising edge of the associated rclk by default and may be enabled to be sampled on the falling edge of the associated rclk by setting the rfall bit in the ds3/e3 master receive line options register. rneg/rlcv[3] rneg/rlcv[2] rneg/rlcv[1] input p3 t3 w2 negative input pulse (rneg[3:1]). rneg[3:1] represent the negative pulses received on the b3zs- encoded ds3s or hdb3-encoded e3s when dual rail input format is selected. line code violation (rlcv[3:1]). rlcv[3:1] represent receive line code violations when single rail input format is selected. rneg[3:1] and rlcv[3:1] are sampled on the rising edge of the associated rclk by default and may be enabled to be sampled on the falling edge of rclk by setting the rfall bit in the ds3/e3 master receive line options register. tclk[3] tclk[2] tclk[1] output r3 v1 w3 transmit clock (tclk[3:1]). tclk[3:1] provide timing for circuitry downstream of the ds3 and e3 transmitters of the temap-84. tclk[3:1] are nominally 44.736 mhz or 34.368 mhz, 50% duty cycle clocks.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 29 pin name type pin no. function tpos/tdat[3] tpos/tdat[2] tpos/tdat[1] output r2 u2 aa1 transmit positive pulse (tpos[3:1]). tpos[3:1] represent the positive pulses transmitted on the b3zs- encoded ds3 or hdb3-encoded e3 lines when dual- rail output format is selected. transmit data output (tdat[3:1]). tdat[3:1] represent the nrz (unipolar) ds3 output data streams when single rail output format is selected. tpos[3:1] and tdat[3:1] are updated on the falling edge of the associated tclk by default but may be enabled to be updated on the rising edge of the associated tclk by setting the trise bit in the ds3/e3 master transmit line options register. tpos[3:1] and tdat[3:1] are updated on ticlk[3:1] rather than tclk[3:1] when the ticlk bit in the ds3/e3 master transmit line options register is set. tneg/tmfp[3] tneg/tmfp[2] tneg/tmfp[1] output u4 w1 ab1 transmit negative pulse (tneg[3:1]). tneg[3:1] represent the negative pulses transmitted on the b3zs-encoded ds3 or hdb3-encoded e3 lines when dual-rail output format is selected. transmit multiframe pulse (tmfp[3:1]). these signals mark the transmit frame alignment when configured for single rail operation. tmfp[3:1] indicate the position of overhead bits in the transmit transmission system stream, tdat[3:1]. tmfp[3:1] are high during the first bit (x1) of the multiframe or e3 frame. tneg[3:1] and tmfp[3:1] are updated on the falling edge of the associated tclk by default but may be enabled to be updated on the rising edge of the associated tclk by setting the trise bit in the ds3/e3 master transmit line options register. tneg[3:1] and tmfp[3:1] are updated on ticlk[3:1] rather than tclk[3:1] when the ticlk bit in the ds3/e3 master transmit line options register is set. ticlk[3] ticlk[2] ticlk[1] input t4 v4 y2 transmit input clock (ticlk[3:1]). ticlk[3:1] provides the transmit direction timing for the three ds3s or e3s. ticlk[3:1] are nominally 44.736 mhz or 34.368 mhz, 50% duty cycle clocks.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 30 pin name type pin no. function ds3 and e3 system side interface rgapclk/rsclk [3] rgapclk/rsclk [2] rgapclk/rsclk [1] output h4 l3 n3 framer recovered gapped clock (rgapclk[3:1]). rgapclk[3:1] are valid when the temap-84 is configured as ds3 or e3 framers by setting the opmode_spex[2:0] bits in the spe configuration registers and the rxgapen bit in the ds3 and e3 master unchannelized interface options register. rgapclk[x] is the recovered clock and timing reference for rdato[x]. rgapclk[3:1] are held either high or low during bit positions which correspond to overhead. framer recovered clock (rsclk[3:1]). rsclk[3:1] are valid when the temap-84 is configured as ds3 or e3 framers by setting the opmode_spex[2:0] bits in the spe configuration registers. rsclk[3:1] are the recovered clocks and timing references for rdato[3:1], rfpo/rmfpo[3:1], and rovrhd[3:1]. rdato[3] rdato[2] rdato[1] output h2 k4 n2 framer receive data (rdato[3:1]). rdato[3:1] are valid when the temap-84 is configured as ds3 or e3 framers by setting the opmode_spex[2:0] bits in the spe configuration registers. rdato[3:1] are the received data aligned to rfpo/rmfpo[3:1] and rovrhd[3:1]. rdato[3:1] are updated on either the falling or rising edge of the associated rgapclk or rsclk, depending on the value of the rsclkr bit in the ds3 and e3 master unchannelized interface options register. by default, rdato[3:1] will be updated on the falling edge of the associated rgapclk[3:1] or rsclk[3:1].
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 31 pin name type pin no. function rfpo/rmfpo[3] rfpo/rmfpo[2] rfpo/rmfpo[1] output h1 k2 m2 framer receive frame pulse/multi-frame pulse (rfpo/rmfpo[3:1]). rfpo/rmfpo[3:1] are valid when the temap-84 is configured to be in framer only mode by setting the opmode_spex[2:0] bits in the spe configuration registers. rfpo[3:1] are aligned to rdato[3:1] and indicate the position of the first bit in each ds3 m-subframe and the first bit in each g.751 e3 or g.832 e3 frame. rmfpo[3:1] are aligned to rdato[3:1] and indicate the position of the first bit in each ds3 m-frame and the first bit in each g.751 or g.832 e3 frame. this is selected by setting the rxmfpo bit in the ds3 and e3 master unchannelized interface options registers. rfpo/rmfpo[3:1] are updated on either the falling or rising edge of the associated rsclk depending on the setting of the rsclkr bit in the ds3 and e3 master unchannelized interface options register. rovrhd[3] rovrhd[2] rovrhd[1] output h3 k1 n1 framer receive overhead (rovrhd[3:1]). rovrhd[3:1] are valid when the temap-84 is configured as ds3 or e3 framers by setting the opmode_spex[2:0] bits in the spe configuration registers. rovrhd[3:1] will be high whenever the data on rdato[3:1] corresponds to an overhead bit position. rovrhd[3:1] is updated on the either the falling or rising edge of the associated rsclk depending on the setting of the rsclkr bit in the ds3 and e3 master unchannelized interface options register.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 32 pin name type pin no. function tfpo/tmfpo/ tgapclk[3] tfpo/tmfpo/ tgapclk[2] tfpo/tmfpo/ tgapclk[1] output f4 j4 m3 framer transmit frame pulse/multi-frame pulse reference (tfpo/tmfpo[3:1]). tfpo/tmfpo[3:1] are valid when the temap-84 is configured as ds3 framers by setting the opmode_spex[2:0] bits in the spe configuration registers and setting the txgapen bit to 0 in the ds3 and e3 master unchannelized interface options register. in ds3 mode, tfpo[3:1] pulse high for 1 out of every 85 clock cycles, giving a reference m-subframe indication. in e3 mode, tfpo[3:1] pulse high to mark the first bit of the frame. in ds3 mode, tmfpo[3:1] pulse high for 1 out of every 4760 clock cycles, giving a reference m-frame indication. tmfpo[3:1] behaves the same as tfpo[3:1] for e3 applications. this is selected by setting the txmfpo bit in the ds3 and e3 master unchannelized interface options registers. tfpo/tmfpo[3:1] will be updated on the falling edge of ticlk when the associated tdatifall register bit is a logic 0 and on the rising edge when tdatifall is a logic 1. framer gapped transmit clock (tgapclk[3:1]). tgapclk[3:1] are valid when the temap-84 is configured as ds3 framers by setting the opmode_spex[2:0] bits in the spe configuration registers and setting the txgapen bit to 1 in the ds3 and e3 master unchannelized interface options register. tgapclk[3:1] are derived from the transmit reference clocks ticlk[3:1] or from the receive clock if loop- timed. the overhead bit (gapped) positions are generated internal to the device. tgapclk[3:1] are held high during the overhead bit positions. this clock is useful for interfacing to devices which source payload data only. tgapclk[3:1] are used to sample the associated tdati[3:1] inputs.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 33 pin name type pin no. function tdati[3] tdati[2] tdati[1] input g2 j3 l2 framer transmit data (tdati[3:1]). tdati[3:1] contain the serial data to be transmitted when the temap-84 is configured as ds3 framers by setting the opmode_spex[2:0] bits in the spe configuration registers. tdati[3:1] are sampled on the rising edge of the associated ticlk if the txgapen bit in the ds3 and e3 master unchannelized interface options register is logic 0. if txgapen is logic 1, then tdati[3:1] are sampled on the rising edge of tgapclk. tdati[3:1] can be configured to be sampled on the falling edge of the associated ticlk or tgapclk by setting the tdatifall bit in the ds3 and e3 master unchannelized interface options register. tfpi/tmfpi[3] tfpi/tmfpi[2] tfpi/tmfpi[1] input g1 j1 m1 framer transmit frame pulse/multiframe pulse (tfpi/tmfpi[3:1]). tfpi/tmfpi[3:1] are valid when the temap-84 is configured as ds3 or e3 framers by setting the opmode_spex[2:0] bits in the spe configuration registers. tfpi[3:1] indicate the position of all overhead bits in each ds3 m-subframe or the first bit in each g.751 e3 or g.832 e3 frame. tfpi[3:1] are not required to pulse at every overhead bit. tmfpi[3:1] indicate the position of the first bit in each 4760-bit ds3 m-frame or the first bit in each e3 frame. tmfpi[3:1] are not required to pulse at every multiframe boundary. this is selected by setting the txmfpi bit in the ds3 and e3 master unchannelized interface options registers. tfpi/tmfpi[3:1] are sampled on the rising edge of the associated ticlk. tdati[3:1] can be configured to be sampled on the falling edge of the associated ticlk by setting the tdatifall bit to 1 in the ds3 and e3 master unchannelized interface options register.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 34 pin name type pin no. function flexible bandwidth ports port #1 is associated with sbi spe #1. port #2 is associated with sbi spe #2. port #3 is associated with sbi spe #3. ifbwclk[3] ifbwclk[2] ifbwclk[1] input n22 k19 h19 the ingress flexible bandwidth clocks (ifbwclk[3:1]). the ifbwclk[3:1] clocks provide the timing for an arbitrary bandwidth payload to be inserted into the system drop bus (sddata[7:0]). each clock is associated with one spe and is only used when the associated spe is configured to carry a fractional payload by the opmode_spex[2:0] bits of the spe configuration registers. ifbwclk[3:1] may have a maximum frequency of 51.84 mhz and may be gapped if required. each ifbwclk samples the associated ifbwdat[3:1] and ifbwen[3:1] inputs on the rising edge. ifbwdat[3] ifbwdat[2] ifbwdat[1] input n20 l20 j20 the ingress flexible bandwidth data (ifbwdat[3:1]). these inputs present bit serial data for insertion into the system drop bus (sddata[7:0]). only bits for which the associated ifbwen input is sampled high are accepted. each data input is associated with one spe and is only used when the associated spe is configured to carry a fractional payload by the opmode_spex[2:0] bits of the spe configuration registers. ifbwdat[3:1] are sampled on the rising edge of the associated ifbwclk input. ifbwen[3] ifbwen[2] ifbwen[1] input p19 l22 j21 the ingress flexible bandwidth enables (ifbwen[3:1]). a logic high on any of these inputs indicates a valid bit on the associated ifbwdat input. the ifbwen[3:1] inputs are constrained such that the maximum data rate of each of ifbwdat[3:1] is less than 49.72 mbit/s. ifbwen[3:1] are sampled on the rising edge of the associated ifbwclk input.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 35 pin name type pin no. function efbwclk[3] efbwclk[2] efbwclk[1] input p22 m22 j22 the egress flexible bandwidth clocks (efbwclk[3:1]). the efbwclk[3:1] clocks provide the timing for an arbitrary bandwidth payload extracted from the system add bus (sadata[7:0]). each clock is associated with one spe and is only used when the associated spe is configured to carry a fractional payload by the opmode_spex[2:0] bits of the spe configuration registers. efbwclk[3:1] may have a maximum frequency of 51.84 mhz and may be gapped if required. each efbwclk samples the associated ebwdreq on the rising edge and updates the associated efbwdat] and efbwen on the falling edge. efbwdreq[3] efbwdreq[2] efbwdreq[1] input p21 m21 j19 the egress flexible bandwidth data requests (efbwreq[3:1]). the data request input must be asserted high for a efbwclk cycle for each bit of data required. in response to sampling efwbdreq[3:1] high, the associated efbwdat output will either present an available bit a cycle later with an accompanying assertion of the associated efbwen or ignore the request if no data is ready. in many applications (eg. frame relay and atm), every request will be acknowledged with data. in applications where the source data is fixed, it is permissible to hold efbwdreq[3:1] high, in which case efbwen identifies valid bytes. efbwdreq[3:1] are sampled on the rising edge of the associated efbwclk input.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 36 pin name type pin no. function efbwdat[3] efbwdat[2] efbwdat[1] output f21 b22 a19 the egress flexible bandwidth data (efbwdat[3:1]). these outputs present bit serial data extracted from the system add bus (sadata[7:0]). only bits for which the associated efbwen output is simultaneously high are valid. each data input is associated with one spe and is only used when the associated spe is configured to carry a fractional payload by the opmode_spex[2:0] bits of the spe configuration registers. efbwdat[3:1] are updated on the falling edge of the associated efbwclk input. efbwen[3] efbwen[2] efbwen[1] output e22 d20 b18 the egress flexible bandwidth enables (efbwen[3:1]). a logic high on any of these outputs indicates a valid bit on the associated efbwdat output. the efbwen[3:1] will only be asserted, with a one cycle latency, in response to a sampled logic high on the associated efbwdreq, and then only if data is available for presenting on the associated efbwdat. efbwen[3:1] are updated on the falling edge of the associated efbwclk input. recovered t1 and e1 clocks recvclk1 output f2 recovered clock 1 (recvclk1). this clock output is a recovered and de-jittered clock from any one of the 84 1.544 mbit/s or 63 2.048mbit/s tributaries. recvclk2 output e4 recovered clock 2 (recvclk2). this clock output is a recovered and de-jittered clock from any one of the 84 1.544 mbit/s or 63 2.048mbit/s tributaries. recvclk3 output g3 recovered clock 3 (recvclk3). this clock output is a recovered and de-jittered clock from any one of the 84 1.544 mbit/s or 63 2.048mbit/s tributaries.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 37 pin name type pin no. function xclk_t1 input e2 t1 crystal clock input (xclk_t1). this input clocks the digital phase locked loop that performs jitter attenuation on the t1 recovered clocks which drive the recvclk1/2/3 outputs. xclk_t1 is nominally a 37.056 mhz 32ppm, 50% duty cycle clock. this input may be tied to ground in applications that do not use the recvclk1/2/3 outputs as 1.544 mhz clocks. xclk_e1 input f3 e1 crystal clock input (xclk_e1). this input clocks the digital phase locked loop that performs jitter attenuation on the e1 recovered clocks which drive the recvclk1/2/3 outputs. xclk_e1 is nominally a 49.152 mhz 32ppm, 50% duty cycle clock when configured for e1 modes. this input may be tied to ground in applications that do not use the recvclk1/2/3 outputs as 2.048 mhz clocks. telecom line side interface lrefclk input y4 line reference clock (lrefclk). this signal provides reference timing for the sonet telecom bus interface. on the incoming byte interface of the telecom bus, ldc1j1v1, lddata[7:0], lddp, ldpl, ldtpl, ldv5, ldais and lac1 are sampled of the rising edge or lrefclk. in the outgoing byte interface, ladata[7:0], ladp, lapl, lac1j1v1 and laoe/latpl are updated on the rising edge of lrefclk. this clock may be held low if the telecom bus interface is unused. this clock is nominally a 19.44 mhz +/-50ppm or 77.76 mhz +/-50ppm clock with a 50% duty cycle. this clock must be phase locked to srefclk and can be external connected to srefclk.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 38 pin name type pin no. function l77 input aa4 the line 77.76 mhz select input determines the expected frequency of lrefclk. if l77 is low, lrefclk is expected to be 19.44 mhz. if l77 is high, lrefclk is expected to be 77.76 mhz and data is driven and sampled every fourth cycle. l77 must be held static. lac1 input w10 line add c1 frame pulse (lac1). the add bus timing signal identifies the frame and multiframe boundaries on the add data bus ladata[7:0]. lac1 is set high to mark the first c1 byte of the first transport envelope frame of the 4 frame multiframe on the ladata[7:0] bus. lac1 need not be presented on every occurrence of the multiframe . lac1 is sampled on the rising edge of lrefclk. lac1j1v1 output a a11 line add bus composite timing signal (lac1j1v1). the add bus composite timing signal identifies the frame, payload and tributary multiframe boundaries on the line add data bus ladata[7:0]. lac1j1v1 pulses high with the line add payload active signal lapl set low to mark the first sts-1 (stm-0/au3) identification byte or equivalently the stm identification byte c1. optionally the lac1j1v1 signal pulses high with lapl set high to mark the path trace byte j1. optionally the lac1j1v1 signal pulses high on the v1 byte to indicate tributary multiframe boundaries. in a system with multiple temap-84s sharing the same line add bus only one device should have lac1j1v1 connected. all devices must be configured via the txptr[9:0] bits in the sonet/sdh transmit pointer configuration and ttmp telecom interface configuration registers for the same j1 location. when l77 high, lac1j1v1 is only valid (i.e. identifies the first c1, j1 and v1 of the concatenated stm-4 data stream) if the lstm[1:0] bits in the master bus configuration register (0x0006) are set to ?00?. lac1j1v1 is updated on the rising edge of lrefclk.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 39 pin name type pin no. function laoe/latpl output a b11 the latplsel bit of the sonet/sdh master egress vtpp configuration register determines the function of this output. when latplsel is logic 1, the signal is latpl. when latplsel is logic 0, the signal is laoe. line add bus output enable (laoe). the add bus output enable signal is asserted high whenever the line add bus is being driven which is co-coincident with the line add bus outputs coming out of tri-state. this pin is intended to control an external multiplexer when multiple temap-84s are driving the telecom add bus during their individual tributaries. this same function is accomplished with the add bus tristate drivers but increased tolerance to tributary configuration problems is possible with an external mux. this output is controlled via the laoe bit in the ttmp tributary control registers when the egress vtpp is bypassed. when the the egress vtpp is not bypassed or a tu-3 is being mapped, laoe is high. line add bus tributary payload active (ldatpl). the tributary payload active signal marks the bytes carrying the tributary payload. latpl is high during each tributary payload byte on the ladata[7:0] bus. latpl will be low during transport overhead, path overhead, v1 bytes and v2 bytes. to indicate pointer adjustments, latpl will be asserted appropriately during the v3 byte and following byte for the tributary. laoe/latpl is updated on the rising edge of lrefclk.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 40 pin name type pin no. function ladata[0] ladata[1] ladata[2] ladata[3] ladata[4] ladata[5] ladata[6] ladata[7] output tristate w14 y13 a a13 a b13 w13 a a12 w12 w11 line add bus data (ladata[7:0]). the add bus data contains the sonet transmit payload data in byte serial format. all transport overhead bytes are set to 00h. the phase relation of the spe (vc) to the transport frame is determined by the add bus composite timing signal lac1j1v1 and is software programmable to any valid pointer offset. ladata[7] is the most significant bit (corresponding to bit 1 of each serial word, the first bit to be transmitted). by default, ladata[7:0] is only asserted during the sonet/sdh tributaries assigned to this device as determined by the laoe bit in the ttmp tributary control registers. as options, ladata[7:0] can be driven during transport overhead, for all bytes of an stm-1 when configured for 77.76mhz operation or all the time. ladata[7:0] is updated on the rising edge of lrefclk. ladp output tristate a b14 line add bus data parity (ladp). the add bus data parity signal carries the parity of the outgoing signals. the parity calculation encompasses the ladata[7:0] bus and optionally the lac1j1v1 and lapl signals. lac1j1v1 and lapl can be included in the parity calculation by setting the inclac1j1v1 and inclapl register bits in the sonet/sdh master egress configuration register high, respectively. odd parity is selected by setting the laop register bit in the same register high and even parity is selected by setting the laop bit low. by default, ladp is only asserted during the sonet/sdh tributaries assigned to this device as determined by the laoe bit in the ttmp tributary control registers. as options, ladp can be driven during transport overhead, for all bytes of an stm-1 when configured for 77.76mhz operation or all the time. ladp is updated on the rising edge of lrefclk.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 41 pin name type pin no. function lapl output tristate a a14 line add bus payload active (lapl). the add bus payload active signal identifies the payload bytes on ladata[7:0]. lapl is set high during path overhead and payload bytes and low during transport overhead bytes. by default, lapl is only asserted during the sonet/sdh tributaries assigned to this device as determined by the laoe bit in the ttmp tributary control registers. as options, lapl can be driven during transport overhead, for all bytes of an stm-1 when configured for 77.76mhz operation or all the time. lapl is updated on the rising edge of lrefclk. lav5 output tristate w15 line add bus v5 byte (lav5). the outgoing tributary v5 byte signal marks the various tributary v5 bytes. lav5 marks each tributary v5 byte on the ladata[7:0] bus when high. by default, lav5 is only asserted during the sonet/sdh tributaries assigned to this device as determined by the laoe bit in the ttmp tributary control registers. as options, lav5 can be driven during transport overhead, for all bytes of an stm-1 when configured for 77.76mhz operation or all the time. lav5 is updated on the rising edge of lrefclk. lddata[0] lddata[1] lddata[2] lddata[3] lddata[4] lddata[5] lddata[6] lddata[7] input w5 a a6 a b5 y3 y6 a a5 a b4 ab3 line drop bus data (lddata[7:0]). the drop bus data contains the sonet/sdh receive payload data in byte serial format. lddata[7] is the most significant bit, corresponding to bit 1 of each serial word, the bit transmitted first. lddata[7:0] is sampled on the rising edge of lrefclk.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 42 pin name type pin no. function lddp input y7 line drop bus data parity (lddp). the incoming data parity signal carries the parity of the incoming signals. the parity calculation encompasses the lddata[7:0] bus and optionally the ldc1j1v1 and ldpl signals. ldc1j1v1 and ldpl can be included in the parity calculation by setting the incldc1j1v1 and incldpl bits in the sonet/sdh master ingress configuration register high, respectively. odd parity is selected by setting the ldop bit in the master sonet/sdh ingress configuration register high and even parity is selected by setting the ldop bit low. lddp is sampled on the rising edge of lrefclk. ldc1j1v1 input ab6 line drop c1/j1 frame pulse (ldc1j1v1). the input c1/j1 frame pulse identifies the transport envelope and synchronous payload envelope frame boundaries on the incoming sonet stream. ldc1j1v1 is set high while ldpl is low to mark the first c1 byte of the transport envelope frame on the lddata[7:0] bus. ldc1j1v1 is set high while ldpl is high to mark each j1 byte of the synchronous payload envelope(s) on the lddata[7:0] bus. ldc1j1v1 must be present at every occurrence of the first c1 and all j1 bytes. optionally ldc1j1v1 indicates multiframe alignment when high during the first v1 bytes of each envelope. ldc1j1v1 is sampled on the rising edge of lrefclk. ldpl input ab7 line drop bus payload active (ldpl). the payload active signal identifies the bytes on lddata[7:0] that carry payload bytes. ldpl is set high during path overhead and payload bytes and low during transport overhead bytes. ldpl is set high during the h3 byte to indicate a negative pointer justification and low during the byte following h3 to indicate a positive pointer justification event. ldpl is sampled on the rising edge of lrefclk.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 43 pin name type pin no. function ldv5 input w6 line drop bus v5 byte (ldv5). the incoming tributary v5 byte signal marks the various tributary v5 bytes. ldv5 marks each tributary v5 byte on the lddata[7:0] bus when high. the ldv5 input is only used if the ingress vtpp is bypassed (i.e. the ivtppbyp bit of the sonet/sdh master ingress configuration register is logic 1.) ldv5 is sampled on the rising edge of lrefclk. ldtpl input y8 line drop bus tributary payload active (ldtpl). the tributary payload active signal marks the bytes carrying the tributary payload which have been identified by an external payload processor. when this signal is available, the internal pointer processor can be bypassed. ldtpl is only respected for asynchronously mapped tributaries. ldtpl is high during each tributary payload byte on the lddata[7:0] bus. in floating mode, ldtpl contains valid data only for bytes in the vc3 or vc4 virtual containers, or the sts-1 spe. it should be ignored for bytes in the transport overhead. in locked mode, ldtpl is low for transport overhead. ldtpl is sampled on the rising edge of lrefclk. ldais input aa8 line drop bus tributary path alarm indication signal (ldais). the active high tributary path alarm indication signal identifies tributaries on the incoming data stream lddata[7:0] that are in ais state. when this signal is available, the internal pointer processor can be bypassed. ldais is invalid when ldtpl is low. ldais is only respected for asynchronously mapped tributaries. ldais is sampled on the rising edge of lrefclk.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 44 pin name type pin no. function radeastck input w7 remote alarm port east clock (radeastck). the remote serial alarm port east clock provides timing for the east remote serial alarm port. it is nominally a 9.72 mhz clock, but can range from 1.344 mhz to 10 mhz. inputs radeastfp and radeast are sampled on the rising edge of radeastck. radeastfp input y9 remote alarm port east frame pulse (radeastfp). the remote serial alarm port east frame pulse is used to locate the alarm bits of the individual tributaries in the east remote serial alarm port. radeastfp is set high to mark the first bip-2 error bit of tributary tu #1 in tug2 #1 of tug3 #1 carried in radeast. radeastfp must be set high to mark every occurrence of this bit. temap-84 will not flywheel on radeastfp in order to accommodate a variety of radeastck frequencies. radeastfp is sampled on the rising edge of radeastck. radeast input aa9 remote alarm port data east (radeast). the remote serial alarm port east carries the tributary path bip-2 error count, rdi status, and rfi status in the east remote serial alarm port. the first bip-2 error bit of tributary tu #1 in tug2 #1 of tug3 #1 on radeast is marked by a high level on radeastfp. the status carried on radeast is software selectable to be reported by the rdi, rfi and rei alarms and is selectable to be associated with any tributary on the outgoing data stream ladata[7:0]. radeast is sampled on the rising edge of radeastck.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 45 pin name type pin no. function radwestck input w9 remote alarm port west clock (radwestck). the remote serial alarm port west clock provides timing for the west remote serial alarm port. it is nominally a 9.72 mhz clock, but can range from 1.344 mhz to 10 mhz. inputs radwestfp and radwest are sampled on the rising edge of radwestck. radwestfp input y10 remote alarm port west frame pulse (radwestfp). the remote serial alarm port west frame pulse is used to locate the alarm bits of the individual tributaries in the west remote serial alarm port. radwestfp is set high to mark the first bip-2 error bit of tributary tu #1 in tug2 #1 of tug3 #1 carried in radwest. radwestfp must be set high to mark every occurrence of this bit. temap-84 will not flywheel on radwestfp in order to accommodate a variety of radwestck frequencies. radwestfp is sampled on the rising edge of radwestck. radwest input a a10 remote alarm port data west (radwest). the remote serial alarm port west carries the tributary path bip-2 error count, rdi status, and rfi status in the west remote serial alarm port. the first bip-2 error bit of tributary tu #1 in tug2 #1 of tug3 #1 on radwest is marked by a high level on radwestfp. the status carried on radwest is software selectable to be reported by the rdi, rfi and rei alarms and is selectable to be associated with any tributary on the outgoing data stream ladata[7:0]. radwestfp is sampled on the rising edge of radwestck.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 46 pin name type pin no. function clk52m input a b10 52 mhz clock reference (clk52m). the 52mhz clock reference is used to generate a gapped ds3 clock when demapping a ds3 from the sonet stream and also to generate a gapped ds3/e3 clock when receiving a ds3/e3 from the sbi bus interface. this clock has two nominal values.the first is a nominal 51.84 mhz 50% duty cycle clock. the second is a nominal 44.928 mhz 50% duty cycle clock. the expected frequency is determined by the fastclkfreq bit of the sonet/sdh master ds3 clock generation control register. if e3 data rates are being supported, clk52m must be 51.84mhz. scaleable bandwidth interconnect interface ctclk input f19 common transmit clock (ctclk). this input signal is used as a reference transmit tributary clock which can be used in egress clock master modes. ctclk must be multiple of 8 khz. the transmit clock is derived by the jitter attenuator pll using ctclk as a reference. the temap may be configured to ignore the ctclk input and lock to the data or one of the recovered ingress clocks instead, recvclk1, recvclk2 and recvclk3. the receive tributary clock is automatically substituted for ctclk if line loopback or looptiming is enabled. srefclk input c10 system reference clock (srefclk). this system reference clock is a nominal 19.44 mhz +/-50ppm or 77.76 mhz +/-50ppm 50% duty cycle clock. this clock is common to both the add and drop sides of the sbi bus. srefclk must be active for all applications, except ds3/e3 framer only mode when the system interface is serial clock and data. when the sysopt register bits are binary 01 (h-mvip interface), srefclk is required to be 19.44 mhz. when passing transparent virtual tributaries between the telecom bus and the sbi bus, srefclk must be the same as lrefclk.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 47 pin name type pin no. function s77 input d10 the sbi 77.76 mhz select input determines the expected frequency of srefclk. if s77 is low, srefclk is expected to be 19.44 mhz. if s77 is high, srefclk is expected to be 77.76 mhz and data is driven and sampled every fourth cycle. this signal is a don't care when the sysopt register bits are binary 01 (h-mvip interface). in this mode, srefclk is required to be 19.44 mhz. s77 must be held static. sdc1fp i/o b3 sbi drop c1 frame pulse (sdc1fp). the sdc1fp c1 frame pulse synchronizes devices interfacing to the insert sbi bus. the frame pulse indicates sbi bus multiframe alignment which occurs every 500 s, therefore this signal is pulsed every 9720 srefclk cycles (38880 cycles if s77 is high). this signal does not need to occur every sbi multiframe and is also used to indicate t1 and e1 multiframe alignment in synchronous sbi mode by pulsing at multiples of every 12 sbi multiframes (48 t1/e1 frames). in synchronous locked mode, as selected by the syncsbi context bit programmed through the rx-sbi-elst indirect channel data register, sdc1fp pulses every 116640 srefclk cycles (466560 cycles if s77 is high). if the syncsbi bit is logic 1 for at least one tributary, sdc1fp must indicate t1 and e1 multiframe alignment. the temap-84 can be configured to generate this frame pulse. only one device on the sbi bus should generate this signal. by default this signal is not enabled to generate the frame pulse. if a sdc1fp pulse is received at an unexpected cycle, the drop bus with become high-impedence until two consecutive valid sdc1fp pulses occur. the system frame pulse is a single srefclk cycle long and is updated on the rising edge of srefclk.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 48 pin name type pin no. function sac1fp input b11 sbi add c1 frame pulse (sac1fp). the extract c1 frame pulse synchronizes devices interfacing to the extract sbi bus. the frame pulse indicates sbi bus multiframe alignment which occurs every 500 s, therefore this signal is pulsed every 9720 srefclk cycles (38880 cycles if s77 is high). this signal does not need to occur every sbi multiframe.sac1fp is sampled on the rising edge of srefclk. sadata[0] sadata[1] sadata[2] sadata[3] sadata[4] sadata[5] sadata[6] sadata[7] input a11 d12 b12 c12 d13 b13 c13 d14 system add bus data (sadata[7:0]). the system add data bus is a time division multiplexed bus which carries the e1, t1 and ds3 tributary data is byte serial format over the sbi bus structure. this device only monitors the add data bus during the timeslots assigned to this device. sadata[7:0] is sampled on the rising edge of srefclk. sadp input a14 system add bus data parity (sadp). the system add bus signal carries the even or odd parity for the add bus signals sadata[7:0], sapl and sav5. the temap-84 monitors the add bus parity during all cycles when s77 is low and during the entire selected stm-1 when s77 is high. sadp is sampled on the rising edge of srefclk.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 49 pin name type pin no. function sapl input b14 system add bus payload active (sapl). the add bus payload active signal indicates valid data within the sbi bus structure. this signal must be high during all octets making up a tributary. this signal goes high during the v3 or h3 octet of a tributary to indicate negative timing adjustments between the tributary rate and the fixed sbi bus structure. this signal goes low during the octet after the v3 or h3 octet of a tributary to indicate positive timing adjustments between the tributary rate and the fixed sbi bus structure. in the flexible bandwidth configuration, sapl may only be asserted in response to a logic high on the sajust_req. sapl shall be high an equal or less number of cycles than sajust_req. (some applications require an exact one-to-one correspondence.) the temap-84 only monitors the add bus payload active signal during the tributary timeslots assigned to this device. sapl is sampled on the rising edge of srefclk. sav5 input c14 system add bus payload indicator (sav5). the add bus payload indicator locates the position of the floating payloads for each tributary within the sbi bus structure. timing differences between the tributary timing and the synchronous sbi bus are indicated by adjustments of this payload indicator relative to the fixed sbi bus structure. all timing adjustments indicated by this signal must be accompanied by appropriate adjustments in the sapl signal. the temap-84 only monitors the add bus payload indicator signal during the tributary timeslots assigned to this device. sav5 is sampled on the rising edge of srefclk.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 50 pin name type pin no. function sajust_req output tristate a2 system add bus justification request (sajust_req). the justification request signals the link layer device to speed up, slow down or maintain the rate which it is sending data to the temap-84. this is only used when the temap-84 is the timing master for the tributary transmit direction. this active high signal indicates negative timing adjustments when asserted high during the v3 or h3 octet of the tributary. in response to this the link layer device sends an extra byte in the v3 or h3 octet of the next sbi bus multi-frame. positive timing adjustments are requested by asserting justification request high during the octet following the v3 or h3 octet. the link layer device responds to this request by not sending an octet during the v3 or h3 octet of the next multi-frame. sajust_req has a different significance in the flexible bandwidth mode. in this mode, sajust_req is high for one srefclk cycle for each byte that can be accepted. a valid byte on sadata[7:0] with an accompanying sapl assertion is expected in response. the temap-84 only drives the justification request signal during the tributary timeslots assigned to this device. when operating in 19.44 mhz mode (i.e. s77 low), sajust_req is aligned by the sac1fp input. when operating in 77.76 mhz mode (i.e. s77 high), sajust_req?s alignment is relative to the sdc1fp signal. sajust_req is updated on the rising edge of srefclk.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 51 pin name type pin no. function sddata[0] sddata[1] sddata[2] sddata[3] sddata[4] sddata[5] sddata[6] sddata[7] output tristate c5 a4 b5 c6 a5 b6 c7 d6 system drop bus data (sddata[7:0]). the system drop data bus is a time division multiplexed bus which carries the e1, t1 and ds3 tributary data is byte serial format over the sbi bus structure. this device only drives the data bus during the timeslots assigned to this device. sddata[7:0] is updated on the rising edge of srefclk. sddp output tristate a6 system drop bus data parity (sddp). the system drop bus signal carries the even or odd parity for the drop bus signals sddata[7:0], sdpl and sdv5. whenever the temap-84 drives the data bus, the parity is valid. sddp is updated on the rising edge of srefclk. sdpl output tristate a7 system drop bus payload active (sdpl). the payload active signal indicates valid data within the sbi bus structure. this signal is asserted during all octets making up a tributary. this signal goes high during the v3 or h3 octet of a tributary to accommodate negative timing adjustments between the tributary rate and the fixed sbi bus structure. this signal goes low during the octet after the v3 or h3 octet of a tributary to accommodate positive timing adjustments between the tributary rate and the fixed sbi bus structure. in the flexible bandwidth configuration, sdpl is asserted for each byte as it becomes available. therefore, sdpl may be high or low arbitrarily during any srefclk cycle. the temap-84 only drives the payload active signal during the tributary timeslots assigned to this device. sdpl is updated on the rising edge of srefclk.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 52 pin name type pin no. function sdv5 output tristate c8 system drop bus payload indicator (sdv5). the payload indicator locates the position of the floating payloads for each tributary within the sbi bus structure. timing differences between the tributary timing and the synchronous sbi bus are indicated by adjustments of this payload indicator relative to the fixed sbi bus structure. all timing adjustments indicated by this signal are accompanied by appropriate adjustments in the sdpl signal. the temap-84 only drives the payload indicator signal during the tributary timeslots assigned to this device. sdv5 is updated on the rising edge of srefclk. sbiact output a3 sbi output active (sbiact). the sbi output active indicator is high whenever the temap-84 is driving the sbi drop bus signals. this signal is used by other temap-84s or other sbi devices to detect sbi configuration problems by detecting other devices driving the sbi bus during the same tributary as the device listening to this signal. this output is updated on the rising edge or srefclk. sbidet[0] sbidet[1] input a15 b15 sbi bus activity detection (sbidet[1:0]). the sbi bus activity detect input detects tributary collisions between devices sharing the same sbi bus. each sbi device driving the bus also drives an sbi active signal (sbiact). this pair of activity detection inputs monitors the active signals from two other sbi devices. when unused this signal should be connected to ground. these inputs only have effect when the sbi bus is configured for 19.44mhz (i.e. s77 is low). a collision is detected when either of sbidet[1:0] signals are active concurrently with this device driving sbiact. when collisions occur the sbi drivers are disabled and an interrupt is generated to signal the collision.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 53 pin name type pin no. function microprocessor interface intb output od t21 active low open-drain interrupt (intb). this signal goes low when an unmasked interrupt event is detected on any of the internal interrupt sources. note that intb will remain low until all active, unmasked interrupt sources are acknowledged at their source. csb input a a15 active low chip select (csb). this signal is low during temap-84 register accesses. the csb input has an integral pull up resistor. rdb input w17 active low read enable (rdb). this signal is low during temap-84 register read accesses. the temap-84 drives the d[7:0] bus with the contents of the addressed register while rdb and csb are low. wrb input a b16 active low write strobe (wrb). this signal is low during a temap-84 register write access. the d[7:0] bus contents are clocked into the addressed register on the rising wrb edge while csb is low. d[0] d[1] d[2] d[3] d[4] d[5] d[6] d[7] i/o u22 t20 v19 u21 u20 w22 y22 y21 bidirectional data bus (d[7:0]). this bus provides temap-84 register read and write accesses.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 54 pin name type pin no. function a[0] a[1] a[2] a[3] a[4] a[5] a[6] a[7] a[8] a[9] a[10] a[11] a[12] input a b22 a a21 y19 a a20 a a19 a b20 a a18 w19 a b18 a a17 w18 y16 a a16 address bus (a[12:0]). this bus selects specific registers during temap-84 register accesses. signal a[12] selects between normal mode and test mode register access. a[12] has an integral pull down resistor. tie a[12] directly to ground unless access to bit hizio in test register 0x1000 is required. rstb input w20 active low reset (rstb). this signal provides an asynchronous temap-84 reset. rstb is a schmitt triggered input with an integral pull up resistor. ale input a a22 address latch enable (ale). this signal is active high and latches the address bus a[12:0] when low. when ale is high, the internal address latches are transparent. it allows the temap-84 to interface to a multiplexed address/data bus. the ale input has an integral pull up resistor. jtag interface tck input b1 test clock (tck). this signal provides timing for test operations that can be carried out using the ieee p1149.1 test access port. tms input d2 test mode select (tms). this signal controls the test operations that can be carried out using the ieee p1149.1 test access port. tms is sampled on the rising edge of tck. tms has an integral pull up resistor. tdi input e3 test data input (tdi). this signal carries test data into the temap-84 via the ieee p1149.1 test access port. tdi is sampled on the rising edge of tck. tdi has an integral pull up resistor.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 55 pin name type pin no. function tdo output d1 test data output (tdo). this signal carries test data out of the temap-84 via the ieee p1149.1 test access port. tdo is updated on the falling edge of tck. tdo is a tri-state output which is inactive except when scanning of data is in progress. trstb input c1 active low test reset (trstb). this signal provides an asynchronous temap-84 test access port reset via the ieee p1149.1 test access port. trstb is a schmitt triggered input with an integral pull up resistor. trstb must be asserted during the power up sequence. note that if not used, trstb must be connected to the rstb input. power and ground pins vdd3.3[19] vdd3.3[18] vdd3.3[17] vdd3.3[16] vdd3.3[15] vdd3.3[14] vdd3.3[13] vdd3.3[12] vdd3.3[11] vdd3.3[10] vdd3.3[9] vdd3.3[8] vdd3.3[7] vdd3.3[6] vdd3.3[5] vdd3.3[4] vdd3.3[3] vdd3.3[2] vdd3.3[1] power a18 a22 a b17 d11 d16 d4 e1 f20 l1 l19 r21 r4 v2 w16 w4 w8 y18 y20 y5 power (vdd3.3[19:1]). the vdd3.3[19:1] pins should be connected to a well decoupled +3.3v dc power supply.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 56 pin name type pin no. function vdd1.8[19] vdd1.8[18] vdd1.8[17] vdd1.8[16] vdd1.8[15] vdd1.8[14] vdd1.8[13] vdd1.8[12] vdd1.8[11] vdd1.8[10] vdd1.8[9] vdd1.8[8] vdd1.8[7] vdd1.8[6] vdd1.8[5] vdd1.8[4] vdd1.8[3] vdd1.8[2] vdd1.8[1] power c2 d3 j2 r1 u3 a b2 a b9 y12 y15 a b19 n4 v20 u19 n21 k21 c22 c18 a13 b7 power (vdd1.8[19:1]). the vdd1.8[19:1] pins should be connected to a well-decoupled +1.8v dc power supply.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 57 pin name type pin no. function vss[87] vss[86] vss[85] vss[84] vss[83] vss[82] vss[81] vss[80] vss[79] vss[78] vss[77] vss[76] vss[75] vss[74] vss[73] vss[72] vss[71] vss[70] vss[69] vss[68] vss[67] vss[66] vss[65] vss[64] vss[63] vss[62] vss[61] vss[60] vss[59] vss[58] vss[57] vss[56] vss[55] vss[54] vss[53] vss[52] vss[51] vss[50] vss[49] ground a a2 a a3 a a7 a b8 a b12 a b15 a b21 a10 a12 a16 a17 b4 b10 b16 c11 c15 c17 c19 c3 c4 d15 d19 d22 d5 d8 f1 g4 g19 h20 h21 h22 j10 j11 j12 j13 j14 j9 k10 k11 ground (vss3.3[69:1]). the vss[69:1] pins should be connected to gnd.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 58 pin name type pin no. function vss[48] vss[47] vss[46] vss[45] vss[44] vss[43] vss[42] vss[41] vss[40] vss[39] vss[38] vss[37] vss[36] vss[35] vss[34] vss[33] vss[32] vss[31] vss[30] vss[29] vss[28] vss[27] vss[26] vss[25] vss[24] vss[23] vss[22] vss[21] vss[20] vss[19] vss[18] vss[17] vss[16] vss[15] vss[14] vss[13] vss[12] vss[11] vss[10] vss[9] vss[8] vss[7] k12 k13 k14 k3 k9 k20 k22 l10 l11 l12 l13 l14 l21 l9 m10 m11 m12 m13 m14 m19 m4 m9 m20 n10 n11 n12 n13 n14 n9 n19 p10 p11 p12 p13 p14 p9 p20 r19 r20 r22 t2 t22
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 59 pin name type pin no. function vss[6] vss[5] vss[4] vss[3] vss[2] vss[1] v21 v22 w21 y11 y14 y17 unused unused a1 a8 a9 a20 a21 b2 b8 b9 b17 b19 b20 b21 c9 c16 c20 c21 d7 d9 d17 d18 d21 e19 e20 e21 f22 g20 g21 g22 l4 p4 t19 these balls must be left floating.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 60 notes on pin descriptions: 1. all temap-84 inputs and bi-directionals present minimum capacitive loading and operate at ttl logic levels. 2. all temap-84 outputs and bi-directionals have at least 2 ma drive capability. the bidirectional data bus outputs, d[7:0], have 4 ma drive capability. the outputs tclk[3:1], tpos/tdat[3:1], tneg/tmfp[3:1], rgapclk/rsclk[3:1], rdato[3:1], rfpo/rmfpo[3:1], rovrhd[3:1], tfpo/tmfpo/tgapclk[3:1], sbiact, laoe/latpl, recvclk1, recvclk2 and intb have 4 ma drive capability. the sbi outputs and telecom bus outputs, sddata[7:0], sddp, sdpl, sdv5, sajust_req, sac1fp, lav5, lac1j1v1, ladata[7:0], ladp and lapl, have 8ma drive capability. the bidirectional sbi signal sdc1fp has 8ma drive capability. 3. inputs csb, rstb, ale, tms, tdi and trstb have internal pull-up resistors. 4. input a[12] has an internal pull-down resistor. 5. all unused inputs should be connected to ground. 6. power to the vdd3.3 pins should be applied before power to the vdd1.8 pins is applied. similarly, power to the vdd1.8 pins should be removed before power to the vdd3.3 pins is removed.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 61 9 functional description the temap-84 supports a total throughput of 155.52mbit/s (including overhead) in both transmit (a.k.a. egress) and receive (a.k.a. ingress) directions. the bandwidth is divided into three approximately equal data streams, each independently configured relative to the others. configurations include, but are not limited to: ? 28 1.544 mbit/s or 21 2.048 mbit/s tributaries multiplexed into a ds3 or mapped into a sonet/sdh structure. ? a single 44.736mbit/s or 34.386mbit/s stream. it may be a t3, e3 or clear channel. the 44.736mbit/s data stream may be mapped into a sonet/sdh structure. 9.1 transparent virtual tributaries transparent virtual tributaries (tvts) are supported when performing vt1.5/tu11 or vt2/tu12 mapping into the telecom bus and the sbi bus is being used. conceptually, a tvt is passed straight from the telecom bus to the sbi bus (and visa versa) with no knowledge of the mapping protocol or t1/e1 framing. on the sbi add bus there are two methods of indicating transmit pointers. if the etvtptrbyp or eptrbyp bit is logic 1, the sav5 input must indicate the location of the v5 byte and the v1/v2 bytes need not be valid at the sbi add bus. if both etvtptrbyp and eptrbyp bit are logic 0, the v1/v2 bytes at the sbi add bus must contain a pointer to the v5 byte. if the egress vtpp is bypassed (i.e. evtppbyp bit logic 1), the entire virtual tributary including v1-v5 is transferred without modification. the lav5 output reflects the byte position indicated by the sav5 input. alternately, the v1/v2 bytes may be required to contain a valid pointer. when the egress vtpps are not bypassed, both a new v1/v2 value is encoded and a lav5 output pulse is generated to match. the configuration of the ingress vtpp determines the requirements for the telecom drop bus. if the ingress vtpp is bypassed (i.e. ivtppbyp is logic 1), the j1 byte must be at pointer 522 decimal, the ldv5 input must indicate the location of the v5 byte, encoding of v1/v2 is purely discretionary and the entire virtual tributary including v1-v5 is transferred without modification. if ivtppbyp is logic 0, v1/v2 must contain a valid pointer. the v1/v2 will be modified in the process of mapping the tvt into the sbi drop bus, which by definition has a spe alignment equivalent to a pointer of 522 decimal. if ivtppbyp is logic 0, tributary and path pointer justifications on the telecom drop bus will result in
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 62 corresponding rate justifications at the sbi drop bus as indicated by the sdpl signal. regardless of the ivtppbyp bit state, the sdv5 output will always indicate the v5 byte location. 9.2 the tributary indexing the temux-84 is capable of transporting 84 1.544 mbit/s (t1) or 63 2.048 mbit/s (e1) tributaries. this section explains the correspondence between the indexing systems of the various mapping and multiplexing formats: sbi bus, telecom bus and m13. the listed index systems are used throughout the document. the sbi bus tributary designation uses two integers: the first represents the byte interleaved spe number (range 1 to 3) and the second is the link index within the spe (range 1 to 28). the telecom bus indexing follows the conventions of the itu-t multiplexing structure. the bandwidth is divided into three tug-3s numbered 1 through 3, each of which is composed of seven tug-2s numbered 1 through 7, each of which is composed of either three tu-12s numbered 1 through 3 or four tu-11s numbered 1 through 4. the three ds3s are divided into seven ds2s, each of which is composed of either four 1.544 mbit/s or three 2.048 mbit/s tributaries. the payload capacity is divided into three equal portions. each of the following lists represents one set of equivalent tributaries: ? spe #1, tug-3 #1 and ds3 #1 ? spe #2, tug-3 #2 and ds3 #2 ? spe #3, tug-3 #3 and ds3 #3 table 13 and table 14 provide the equivalencies between the various multiplex and mapping formats. alternately, the formats can be equated with the following formulae: 1.544mbit/s sbi link # = 7*(tu11-1) + tug2 = 4*(ds2-1)+ds1 2.048mbit/s sbi link # = 7*(tu12-1) + tug2 = 3*(ds2-1)+e1
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 63 table 13 - indexing for 1.544 mbit/s tributaries sbi bus spe, link telecom bus tug-3, tug-2, tu11 m13 ds3, ds2, ds1 1,1 1,1,1 1,1,1 1,2 1,2,1 1,1,2 1,3 1,3,1 1,1,3 1,4 1,4,1 1,1,4 1,5 1,5,1 1,2,1 1,6 1,6,1 1,2,2 1,7 1,7,1 1,2,3 1,8 1,1,2 1,2,4 1,9 1,2,2 1,3,1 1,10 1,3,2 1,3,2 1,11 1,4,2 1,3,3 1,12 1,5,2 1,3,4 1,13 1,6,2 1,4,1 1,14 1,7,2 1,4,2 1,15 1,1,3 1,4,3 1,16 1,2,3 1,4,4 1,17 1,3,3 1,5,1 1,18 1,4,3 1,5,2 1,19 1,5,3 1,5,3 1,20 1,6,3 1,5,4 1,21 1,7,3 1,6,1 1,22 1,1,4 1,6,2 1,23 1,2,4 1,6,3 1,24 1,3,4 1,6,4 1,25 1,4,4 1,7,1 1,26 1,5,4 1,7,2 1,27 1,6,4 1,7,3 1,28 1,7,4 1,7,4 2,1 2,1,1 2,1,1 ... ... ...
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 64 table 14 - indexing for 2.048 mbit/s tributaries sbi bus spe, link telecom bus tug-3, tug-2, tu12 m13 ds3, ds2, e1 1,1 1,1,1 1,1,1 1,2 1,2,1 1,1,2 1,3 1,3,1 1,1,3 1,4 1,4,1 1,2,1 1,5 1,5,1 1,2,2 1,6 1,6,1 1,2,3 1,7 1,7,1 1,3,1 1,8 1,1,2 1,3,2 1,9 1,2,2 1,3,3 1,10 1,3,2 1,4,1 1,11 1,4,2 1,4,2 1,12 1,5,2 1,4,3 1,13 1,6,2 1,5,1 1,14 1,7,2 1,5,2 1,15 1,1,3 1,5,3 1,16 1,2,3 1,6,1 1,17 1,3,3 1,6,2 1,18 1,4,3 1,6,3 1,19 1,5,3 1,7,1 1,20 1,6,3 1,7,2 1,21 1,7,3 1,7,3 2,1 2,1,1 2,1,1 ... ... ... clock and frame synchronization constraints section indicates constraints on bus alignments imposed by tvt support. 9.3 t1 performance monitoring t1 framing can be performed on up to three sets of 28 tributaries for the purpose of performance monitoring. the ingress or egress path may be monitored, as selected on an individual tributary basis. the t1 framing function searches for the framing bit pattern in the standard superframe (sf), slc ? 96 or extended superframe (esf) framing formats. when searching for frame each of the 193 (sf or slc ? 96) or each of the 772 (esf) framing bit candidates is simultaneously examined.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 65 the time required to acquire frame alignment to an error-free ingress stream, containing randomly distributed channel data (i.e. each bit in the channel data has a 50% probability of being 1 or 0), is dependent upon the framing format. for sf format, the t1 framer will determine frame alignment within 4.4ms 99 times out of 100. for slc?96 format, the t1 framer will determine frame alignment within 13ms. for esf format, the t1 framer will determine frame alignment within 15 ms 99 times out of 100. once the t1 framer has found frame, the ingress data is continuously monitored for framing bit errors, bit error events (a framing bit error in sf or a crc-6 error in esf), and severely errored framing events. the performance data is accumulated for each tributary. the t1 framer also detects out-of-frame, based on a selectable ratio of framing bit errors. 9.3.1 inband code detection the framer detects the presence of either of two programmable inband loopback activate and deactivate code sequences in either framed or unframed data streams (whether data stream is framed or unframed is not programmable) . the loopback codes will be detected in the presence of a mean bit error rate of up to 10 -2 . when the inband code is framed, the framing bits overwrite the code bits, thus appearing to the receiver as a 2.6x10 -3 ber (which is within the tolerable ber of 10 -2) . code indication is provided on the active high loopback activate (lba) and loopback deactivate (lbd) status bits. changes in these status bits result in the setting of corresponding interrupt status bits, lbai and lbdi respectively, and can also be configured to result in the setting of a maskable interrupt indication. the inband loopback activate condition consists of a repetition of the programmed activate code sequence in all bit positions for a minimum of 5.08 seconds ( 40 ms). the inband loopback deactivate condition consists of a repetition of the programmed deactivate code sequence in all bit positions for a minimum of 5.08 seconds ( 40 ms). programmed codes can be from three to eight bits in length. the code sequence detection and timing is compatible with the specifications defined in t1.403, tr-tsy-000312, and tr-tsy-000303. 9.3.2 t1 bit oriented code detection the presence of 63 of the possible 64 bit oriented codes transmitted in the t1 facility data link channel in esf framing format is detected, as defined in ansi
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 66 t1.403 and in tr-tsy-000194. the 64 th code ( 111111) is similar to the hdlc flag sequence and is used to indicate no valid code received. bit oriented codes are received on the facility data link channel as a 16-bit sequence consisting of 8 ones, a zero, 6 code bits, and a trailing zero (111111110 xxxxxx0). the receiver declares a received c ode valid if it has been observed for two consecutive times the code is declared removed if two code sequences containing code values different from the detected code are received two consecutive times. valid boc are indicated through the boci status bit the boc bits are set to all ones ( 111111) if no valid c ode has been detected. an interrupt is generated to signal when a detected code has been validated, or optionally, when a valid code goes away (i.e. the boc bits go to all ones). 9.3.3 t1 alarm integration the presence of yellow, red, and ais carrier fail alarms (cfa) in sf, slc ? 96 or esf formats is detected and integrated in accordance with the specifications defined in ansi t1.403 and tr-tsy-000191. the presence of yellow alarm is declared when the yellow pattern has been received for 425 ms ( 50 ms); the yellow alarm is removed when the yellow pattern has been absent for 425 ms ( 50 ms). the presence of red alarm is declared when an out-of-frame condition has been present for 2.55 sec ( 40 ms); the red alarm is removed when the out-of-frame condition has been absent for 16.6 sec ( 500 ms). the presence of ais alarm is declared when an out-of- frame condition and all-ones in the pcm data stream have been present for 2.55 sec (40 ms); the ais alarm is removed when the ais condition has been absent for 16.6 sec (500 ms). cfa alarm detection algorithms operate in the presence of a 10 -3 bit error rate. 9.3.3.1 customer interface alarms the rai-ci and ais-ci alarms defined in t1.403 are detected reliably. by definition, rai-ci is a repetitive pattern within the esf data link with a period of 1.08 seconds. it consists of sequentially interleaving 0.99 seconds of 00000000 11111111 (right-to-left) with 90 ms of 00111110 11111111. rai-ci is declared when a bit oriented code of ?00 111110 11111111? is validated (i.e. two consecutive patterns) while rai (a.k.a. yellow alarm) is declared. rai-
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 67 ci is cleared upon deassertion of rai or upon 28 consecutive 40ms intervals without validation of ?00 111110 11111111?. by definition, ais-ci is a repetitive pattern of 1.26 seconds. it consists of 1.11 seconds of an unframed all ones pattern and 0.15 seconds of all ones modified by the ais-ci signature. the ais-ci signature is a repetitive pattern 6176 bits in length in which, if the first bit is numbered bit 0, bits 3088, 3474 and 5790 are logical zeros and all other bits in the pattern are logical ones. ais-ci is an unframed pattern, so it is defined for all framing formats. ais-ci is declared between 1.40 and 2.56 seconds after initiation of the ais-ci signal and is deasserted 16.6 seconds after it ceases. 9.4 e1 performance monitoring e1 framing can be performed on up to three sets of 21 tributaries for the purpose of performance monitoring. the ingress or egress path may be monitored, as selected on an indiividual tributary basis. the e1 framing function searches for basic frame alignment, crc multiframe alignment, and channel associated signaling (cas) multiframe alignment in the incoming recovered pcm stream. once basic (or fas) frame alignment has been found, the incoming pcm data stream is continuously monitored for fas/nfas framing bit errors, which are accumulated in a framing bit error counter dedicated to each tributary. once crc multiframe alignment has been found, the pcm data stream is continuously monitored for crc multiframe alignment pattern errors and crc-4 errors, which are accumulated in a crc error counter dedicated to each tributary. once cas multiframe alignment has been found, the pcm data is continuously monitored for cas multiframe alignment pattern errors. the e1 framer also detects and indicates loss of basic frame, loss of crc multiframe, and loss of cas multiframe, based on user-selectable criteria. the reframe operation can be initiated by software, by excessive crc errors, or when crc multiframe alignment is not found within 400 ms. the e1 framer extracts the contents of the international bits (from both the fas frames and the nfas frames), the national bits, and the extra bits (from timeslot 16 of frame 0 of the cas multiframe). moreover, the framer also extracts submultiframe-aligned 4-bit codewords from each of the national bit positions sa4 to sa8, and stores them in microprocessor-accessible registers that are updated every crc submultiframe. the e1 framer identifies the raw bit values for the remote (or distant frame) alarm (bit 3 in timeslot 0 of nfas frames) and the remote signaling multiframe
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 68 (or distant multiframe) alarm (bit 6 of timeslot 16 of frame 0 of the cas multiframe). access is also provided to the "debounced" remote alarm and remote signaling multiframe alarm bits which are set when the corresponding signals have been a logic 1 for 4 (provided the raic bit is logic 1) and 3 consecutive occurrences, respectively, as per recommendation o.162. detection of ais and timeslot 16 ais are provided. ais is also integrated, and an ais alarm is indicated if the ais condition has persisted for at least 100 ms. the out of frame (oof=1) condition is also integrated, indicating a red alarm if the oof condition has persisted for at least 100 ms. an interrupt may be generated to signal a change in the state of any status bits (inf, insmf, incmf, ais or red), and to signal when any event (rai, rmai, aisd, ts16aisd, cofa, fer, smfer, cmfer, crce or febe) has occurred. additionally, interrupts may be generated every frame, crc submultiframe, crc multiframe or signaling multiframe. basic frame alignment procedure the e1 framer searches for basic frame alignment using the algorithm defined in itu-t recommendation g.706 sections 4.1.2 and 4.2. the algorithm finds frame alignment by using the following sequence: 1. search for the presence of the correct 7-bit fas (?0011011?); 2. check that the fas is absent in the following frame by verifying that bit 2 of the assumed non-frame alignment sequence (nfas) ts 0 byte is a logic 1; 3. check that the correct 7-bit fas is present in the assumed ts 0 byte of the next frame. if either of the conditions in steps 2 or 3 are not met, a new search for frame alignment is initiated in the bit immediately following the second 7-bit fas sequence check. this "hold-off" is done to ensure that new frame alignment searches are done in the next bit position, modulo 512. this facilitates the discovery of the correct frame alignment, even in the presence of fixed timeslot data imitating the fas. the algorithm provides robust framing operation even in the presence of random bit errors; the algorithm provides a 99.98% probability of finding frame alignment within 1 ms in the presence of 10 -3 bit error rate and no mimic patterns. once frame alignment is found, the inf context bit is set to logic 1, a change of frame alignment is indicated (if it occurred), and the frame alignment signal is monitored for errors occurring in the 7-bit fas pattern and in bit 2 of nfas
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 69 frames, and the debounced value of the remote alarm bit (bit 3 of nfas frames) is reported. loss of frame alignment is declared if 3 consecutive fass have been received in error or, additionally, if bit 2 of nfas frames has been in error for 3 consecutive occasions. in the presence of a random 10 -3 bit error rate the frame loss criteria provides a mean time to falsely lose frame alignment of >12 minutes. the e1 framer can be forced to initiate a basic frame search at any time when any of the following conditions are met: ? the software re-frame bit, refr, in the t1/e1 framer indirect channel data registers is set to logic 1; ? the crc frame find block is unable to find crc multiframe alignment; or ? the crc frame find block accumulates excessive crc evaluation errors ( 915 crc errors in 1 second) and is enabled to force a re-frame under that condition. crc multiframe alignment procedure the e1 framer searches for crc multiframe alignment by observing whether the international bits (bit 1 of ts 0) of nfas frames follow the crc multiframe alignment pattern. multiframe alignment is declared if at least two valid crc multiframe alignment signals are observed within 8 ms, with the time separating two alignment signals being a multiple of 2 ms once crc multiframe alignment is found, the incmf register bit is set to logic 1, and the e1 framer monitors the multiframe alignment signal (mfas), indicating errors occurring in the 6-bit mfas pattern, errors occurring in the received crc and the value of the febe bits (bit 1 of frames 13 and 15 of the multiframe). the e1 framer declares loss of crc multiframe alignment if basic frame alignment is lost. however, once crc multiframe alignment is found, it cannot be lost due to errors in the 6-bit mfas pattern. under the crc-to-non-crc interworking algorithm, if the e1 framer can achieve basic frame alignment with respect to the incoming pcm data stream, but is unable to achieve crc-4 multiframe alignment within the subsequent 400 ms, the distant end is assumed to be a non crc-4 interface. the details of this algorithm are illustrated in the state diagram in figure 7.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 70 figure 7 - crc multiframe alignment algorithm fas_find_1 nfas_find fas_find_2 bfa crc to crc interworking fas_find_1_par nfas_find_par fas_find_2_par bfa_par crc to non-crc interworking fas found nfas found next fram e fas found next fram e crcmfa nfas not found next fram e fas not found next fram e fas found nfas not found next fram e fas not found next fram e nfas found next fram e 400ms expire fas found next fram e start 400ms timer and 8ms timer 8ms expire 8ms expire and not(400ms expire) crcmfa_par start 8m s timer reset bfa to most recently found alignment out of frame crcmfa_par ( o p tional settin g) 3 consecutive fasor nfas errors; manual reframe; or excessiv e crc errors
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 71 table 1 - e1 framer framing states state out of frame out of offline frame fas_find_1 yes no nfas_find yes no fas_find_2 yes no bfa no no crc to crc interworking no no fas_find_1_par no yes nfas_find_par no yes fas_find_2_par no yes bfa_par no no crc to non-crc interworking no no the states of the primary basic framer and the parallel/offline framer in the e1 framer block at each stage of the crc multiframe alignment algorithm are shown in table 1. from an out of frame state, the e1 framer attempts to find basic frame alignment in accordance with the fas/nfas/fas g.706 basic frame alignment procedure outlined above. upon achieving basic frame alignment, a 400 ms timer is started, as well as an 8 ms timer. if two crc multiframe alignment signals separated by a multiple of 2 ms are observed before the 8 ms timer has expired, crc multiframe alignment is declared. if the 8 ms timer expires without achieving multiframe alignment, a new offline search for basic frame alignment is initiated. this search is performed in accordance with the basic frame alignment procedure outlined above. however, this search does not immediately change the actual basic frame alignment of the system (i.e., pcm data continues to be processed in accordance with the first basic frame alignment found after an out of frame state while this frame alignment search occurs as a parallel operation). when a new basic frame alignment is found by this offline search, the 8 ms timer is restarted. if two crc multiframe alignment signals separated by a multiple of 2 ms are observed before the 8 ms timer has expired, crc multiframe alignment is declared and the basic frame alignment is set accordingly (i.e., the basic frame alignment is set to correspond to the frame alignment found by the parallel offline search, which is also the basic frame alignment corresponding to the newly found crc multiframe alignment). subsequent expirations of the 8 ms timer will likewise reinitiate a new search for basic frame alignment. if, however, the 400 ms timer expires at any time during this procedure, the e1 framer stops searching for crc multiframe alignment and declares crc-to-non-crc interworking. in this mode, the e1 framer may be
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 72 optionally set to either halt searching for crc multiframe altogether, or may continue searching for crc multiframe alignment using the established basic frame alignment. in either case, no further adjustments are made to the basic frame alignment, and no offline searches for basic frame alignment occur once crc-to-non-crc interworking is declared: it is assumed that the established basic frame alignment at this point is correct. ais detection when an unframed all-ones receive data stream is received, an ais defect is indicated by setting the aisd context bit to logic 1 when fewer than three zero bits are received in 512 consecutive bits or, optionally, in each of two consecutive periods of 512 bits. the aisd bit is reset to logic 0 when three or more zeros in 512 consecutive bits or in each of two consecutive periods of 512 bits. finding frame alignment will also cause the aisd bit to be set to logic 0. e1 alarm integration the oof and the ais defects are integrated, verifying that each condition has persisted for 104 ms ( 6 ms) before indicating the alarm condition. the alarm is removed when the condition has been absent for 104 ms ( 6 ms). the ais alarm algorithm accumulates the occurrences of aisd (ais detection). the e1 framer counts the occurrences of aisd over a 4 ms interval and indicates a valid ais is present when 13 or more aisd indications (of a possible 16) have been received. each interval with a valid ais presence indication increments an interval counter which declares ais alarm when 25 valid intervals have been accumulated. an interval with no valid ais presence indication decrements the interval counter. the ais alarm declaration is removed when the counter reaches 0. this algorithm provides a 99.8% probability of declaring an ais alarm within 104 ms in the presence of a 10 -3 mean bit error rate. the red alarm algorithm monitors occurrences of out of frame (oof) over a 4 ms interval, indicating a valid oof interval when one or more oof indications occurred during the interval, and indicating a valid in frame (inf) interval when no oof indication occurred for the entire interval. each interval with a valid oof indication increments an interval counter which declares red alarm when 25 valid intervals have been accumulated. an interval with valid inf indication decrements the interval counter; the red alarm declaration is removed when the counter reaches 0. this algorithm biases oof occurrences, leading to declaration of red alarm when intermittent loss of frame alignment occurs. the e1 framer can also be disabled to allow reception of unframed data.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 73 9.5 t1/e1 performance data accumulation crc error events, frame synchronization bit error events, and out of frame events, or optionally, change of frame alignment (cofa) events are accumulated with saturating counters over consecutive intervals as defined by the period of the supplied transfer clock signal (typically 1 second). when the transfer clock signal is applied, the counter values are transferred into holding registers and resets the counters to begin accumulating events for the interval. the counters are reset in such a manner that error events occurring during the reset are not missed. if the holding registers are not read between successive transfer clocks, the ovr context bit is asserted to indicate data loss. a bit error event (bee) is defined as an f-bit error for sf and slc ? 96 framing format or a crc-6 error for esf framing format. a framing bit error (fer) is defined as an f s or f t error for sf and slc ? 96 and an f e error for esf framing format. generation of the transfer clock within the temap-84 chip is generated precisely once per second (i.e. 19440000 srefclk cycles) if the autoupdate bit of the t1/e1 framer configuration and status register is logic 1 or by writing to the global pmon update register with the frmr bit set. 9.6 t1/e1 hdlc receiver the hdlc receiver is a microprocessor peripheral used to receive hdlc frames on the 4 khz esf facility data link or the e1 sa-bit data link. a data link can also be extracted from any sub-set of bits within a single ds0. the hdlc receiver detects the change from flag characters to the first byte of data, removes stuffed zeros on the incoming data stream, receives packet data, and calculates the crc-ccitt frame check sequence (fcs). received data is placed into a 128-byte fifo buffer. an interrupt is generated when a programmable number of bytes are stored in the fifo buffer. other sources of interrupt are detection of the terminating flag sequence, abort sequence, or fifo buffer overrun. the rhdl indirect channel data registers contain bits which indicate the overrun or empty fifo status, the interrupt status, and the occurrence end of message bytes written into the fifo. the rhdl indirect channel data registers also indicates the abort, flag, and end of message status of the data just read from the fifo. on end of message, the rhdl indirect channel data registers indicates the fcs status and if the packet contained a non-integer number of bytes.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 74 9.7 t1/e1 receive and transmit digital jitter attenuators the temap-84 contains two separate jitter attenuators, one between the receive demultiplexed or demapped t1 or e1 link and the ingress interface and the other between the egress interface and the transmit t1 or e1 link to be multiplexed into ds3 or mapped into sonet/sdh. each jitter attenuator receives jittered data and stores the stream in a fifo timed to the associated clock. the jitter attenuated data emerges from the fifo timed to the jitter attenuated clock. in the receive jitter attenuator, the jitter attenuated clock is referenced to the demultiplexed or demapped tributary receive clock. in the transmit jitter attenuator, the jitter attenuated transmit tributary clock feeding the m13 multiplexer or sonet/sdh mapper may be referenced to either the data stream, the ctclk primary input, or the tributary receive clock. jitter characteristics the jitter attenuators provide excellent jitter tolerance and jitter attenuation while generating minimal residual jitter. in t1 mode, each jitter attenuator can accommodate up to 48 uipp of input jitter at jitter frequencies above 4 hz. for jitter frequencies below 4 hz, more correctly called wander, the tolerance increases 20 db per decade. in e1 mode each jitter attenuator can accommodate up to 48 uipp of input jitter at jitter frequencies above 5 hz. for jitter frequencies below 5 hz, more correctly called wander, the tolerance increases 20 db per decade. in most applications, each jitter attenuator will limit jitter tolerance at lower jitter frequencies only. the jitter attenuator meet the stringent low frequency jitter tolerance requirements of at&t tr 62411 and itu- t recommendation g.823, and thus allow compliance with these standards and the other less stringent jitter tolerance standards cited in the references. the jitter attenuators exhibit negligible jitter gain for jitter frequencies below 3.4 hz, and attenuates jitter at frequencies above 3.4 hz by 20 db per decade in t1 mode. it exhibits negligible jitter gain for jitter frequencies below 5 hz, and attenuates jitter at frequencies above 5 hz by 20 db per decade in e1 mode. in most applications the jitter attenuators will determine jitter attenuation for higher jitter frequencies only. wander, below 10 hz for example, will essentially be passed unattenuated through the jitter attenuators. jitter, above 10 hz for example, will be attenuated as specified, however, outgoing jitter may be dominated by the waiting time jitter introduced by the multiplexing into ds3 or mapping into sbi or sonet/sdh. the jitter attenuator allows the implied t1 jitter attenuation requirements for a te or nt1 given in ansi standard t1.408, and the implied jitter attenuation requirements for a type ii customer interface given in ansi t1.403 to be met. the jitter attenuator meets the e1 jitter
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 75 attenuation requirements of the itu-t recommendations g.737, g.738, g.739 and g.742. jitter tolerance jitter tolerance is the maximum input phase jitter at a given jitter frequency that a device can accept without exceeding its linear operating range, or corrupting data. for t1 modes the jitter attenuator input jitter tolerance is 48 unit intervals peak-to-peak (uipp) with a worst case frequency offset of 278 hz. for e1 modes the input jitter tolerance is 48 unit intervals peak-to-peak (uipp) with a worst case frequency offset of 369 hz. figure 8 - jitter tolerance t1 modes 0.01 0.1 1.0 10 28 100 1 10 100 1k 10k 100k 0.4 jitter amplitude (ui pp) jitter frequency (hz) acceptable unacceptable 62411min 48 minimum jitter tolerance 4.9 300
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 76 figure 9 - jitter tolerance e1 modes 0.01 0.1 1.0 10 40 100 1 10 100 1k 10k 100k 0.2 jitter amplitude (ui pp) jitter frequency (hz) acceptable unacceptable itu-t g.823 min 48 minimum jitter tolerance 1.5 20 2.4k 18k jitter transfer the output jitter in t1 mode for jitter frequencies from 0 to 3.4 hz is no more than 0.1 db greater than the input jitter, excluding the residual jitter. jitter frequencies above 3.4 hz are attenuated at a level of 20 db per decade, as shown in figure 10.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 77 figure 10 - jitter transfer t1 modes 1 10 100 1k 10k 100k jitter gain (db) jitter frequency (hz) -50 -40 -30 -20 -10 0 43802 max 62411 max 62411 min jitter attenuator response 3.4 20 350 the output jitter in e1 mode for jitter frequencies from 0 to 5.0 hz is no more than 0.1 db greater than the input jitter, excluding the residual jitter. jitter frequencies above 2.5 hz are attenuated at a level of 20 db per decade, as shown in figure 11.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 78 figure 11 -jitter transfer e1 modes 1 10 100 1k 10k 100k jitter gain (db) jitter frequency (hz) -50 -40 -30 -20 -10 0 g.737, g.738, g.739, g.742 max jitter attenuator response 5 unacceptable acceptable 400 40 frequency range the guaranteed linear operating range for the jittered input clock is 1.544 mhz 200 hz with worst case jitter (48 uipp) and maximum srefclk frequency offset ( 50 ppm). the tracking range is 1.544 mhz 997 hz with no jitter or srefclk frequency offset. the guaranteed linear operating range for the jittered input clock is 2.048 mhz 266 hz with worst case jitter (48 uipp) and maximum srefclk frequency offset ( 50 ppm). the tracking range is 2.048 mhz 999 hz with no jitter or srefclk frequency offset.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 79 9.8 t1/e1 pseudo random binary sequence generation and detection (prbs) the pseudo random binary sequence generator/detector (prbs) is a software selectable prbs generator and checker for 2 7 -1, 2 11 -1, 2 15 -1 or 2 20 -1 prbs polynomials for use in the unframed t1 and e1 links. prbs patterns may be generated and monitored in both the transmit or receive directions for all t1 and e1 links simultaneously. the generator is capable of inserting single bit errors under microprocessor control. the detector auto-synchronizes to the expected prbs pattern and accumulates the total number of bit errors in a 16-bit counter. the error count accumulates over the interval defined by writes to the global pmon update register. when a transfer is triggered, the holding register is updated, and the counter reset to begin accumulating for the next interval. the counter is reset in such a way that no events are missed. the data is then available until the next transfer. 9.9 ds3 framer (ds3-frmr) three instances of the ds3 framer are independently programmed. from each the framed data is presented on rdato[x], mapped into the sbi bus or may be demultiplexed to 28 ds1s or 21 e1s (itu-t rec. g.747). the ds3 framer (ds3-frmr) block integrates circuitry required for decoding a b3zs-encoded signal and framing to the resulting ds3 bit stream. the ds3-frmr is directly compatible with the m23 and c-bit parity ds3 applications. the ds3-frmr decodes a b3zs-encoded signal and provides indications of line code violations. the b3zs decoding algorithm and the lcv definition can be independently chosen through software. a loss of signal (los) defect is also detected for b3zs encoded streams. los is declared when inputs rpos and rneg contain zeros for 175 consecutive rclk cycles. los is removed when the ones density on rpos and/or rneg is greater than 33% for 175 1 rclk cycles. the framing algorithm examines five f-bit candidates simultaneously. when at least one discrepancy has occurred in each candidate, the algorithm examines the next set of five candidates. when a single f-bit candidate remains in a set, the first bit in the supposed m-subframe is examined for the m-frame alignment signal (i.e., the m-bits, m1, m2, and m3 are following the 010 pattern). framing is declared, and out-of-frame is removed, if the m-bits are correct for three consecutive m-frames while no discrepancies have occurred in the f-bits. during the examination of the m-bits, the x-bits and p-bits are ignored. the algorithm gives a maximum average reframe time of 1.5 ms.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 80 while the ds3-frmr is synchronized to the ds3 m-frame, the f-bit and m-bit positions in the ds3 stream are examined. an out-of-frame defect is detected when 3 f-bit errors out of 8 or 16 consecutive f-bits are observed (as selected by the m3o8 bit in the ds3 frmr configuration register), or when one or more m-bit errors are detected in 3 out of 4 consecutive m-frames. the m-bit error criteria for oof can be disabled by the mbdis bit in the ds3 framer configuration register. the 3 out of 8 consecutive f-bits out-of-frame ratio provides more robust operation, in the presence of a high bit error rate, than the 3 out of 16 consecutive f-bits ratio. either out-of-frame criteria allows an out-of- frame defect to be detected quickly when the m-subframe alignment patterns or, optionally, when the m-frame alignment pattern is lost. also while in-frame, line code violations, m-bit or f-bit framing bit errors, and p- bit parity errors are indicated. when c-bit parity mode is enabled, both c-bit parity errors and far end block errors are indicated. these error indications, as well as the line code violation and excessive zeros indication, are accumulated over 1 second intervals with the performance monitor (ds3-pmon). note that the framer is an off-line framer, indicating both oof and cofa events. even if an oof is indicated, the framer will continue indicating performance monitoring information based on the previous frame alignment. three ds3 maintenance signals (a red alarm condition, the alarm indication signal, and the idle signal) are detected by the ds3-frmr. the maintenance detection algorithm employs a simple integrator with a 1:1 slope that is based on the occurrence of "valid" m-frame intervals. for the red alarm, an m-frame is said to be a "valid" interval if it contains a red defect, defined as an occurrence of an oof or los event during that m-frame. for ais and idle, an m-frame interval is "valid" if it contains ais or idle, defined as the occurrence of less than 15 discrepancies in the expected signal pattern (1010... for ais, 1100... for idle) while valid frame alignment is maintained. this discrepancy threshold ensures the detection algorithms operate in the presence of a 10 -3 bit error rate. for ais, the expected pattern may be selected to be: the framed "1010" signal; the framed arbitrary ds3 signal and the c-bits all zero; the framed "1010" signal and the c-bits all zero; the framed all-ones signal (with overhead bits ignored); or the unframed all-ones signal (with overhead bits equal to ones). each "valid" m- frame causes an associated integration counter to increment; "invalid" m-frames cause a decrement. with the "slow" detection option, red, ais, or idle are declared when the respective counter saturates at 127, which results in a detection time of 13.5 ms. with the "fast" detection option, red, ais, or idle are declared when the respective counter saturates at 21, which results in a detection time of 2.23 ms (i.e., 1.5 times the maximum average reframe time). red, ais, or idle are removed when the respective counter decrements to 0. ds3 loss of frame detection is provided as recommended by itu-t g.783 with programmable integration periods of 1ms, 2ms, or 3ms. while integrating up to
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 81 assert lof, the counter will integrate up when the framer asserts an out of frame condition and integrates down when the framer de-asserts the out of frame condition. once an lof is asserted, the framer must not assert oof for the entire integration period before lof is deasserted. valid x-bits are extracted by the ds3-frmr to provide indication of far end receive failure (ferf). a ferf defect is detected if the extracted x-bits are equal and are logic 0 (x1=x2=0); the defect is removed if the extracted x-bits are equal and are logic 1 (x1=x2=1). if the x-bits are not equal, the ferf status remains in its previous state. the extracted ferf status is buffered for 2 m- frames before being reported within the ds3 frmr status register. this buffer ensures a better than 99.99% chance of freezing the ferf status on a correct value during the occurrence of an out of frame. when the c-bit parity application is enabled, both the far end alarm and control (feac) channel and the path maintenance data link are extracted. codes in the feac channel are detected by the bit oriented code detector (rboc). hdlc messages in the path maintenance data link are received by the data link receiver (rdlc). the ds3-frmr can be enabled to automatically assert the rai indication in the outgoing transmit stream upon detection of any combination of los, oof or red, or ais. the ds3-frmr can also be enabled to automatically insert c-bit parity febe upon detection of receive c-bit parity error. the ds3-frmr may be configured to generate interrupts on error events or status changes. all sources of interrupts can be masked or acknowledged via internal registers. internal registers are also used to configure the ds3-frmr. access to these registers is via a generic microprocessor bus. 9.10 ds3 bit oriented code detection the presence of 63 of the possible 64 bit oriented codes transmitted in the t1 facility data link channel in esf framing format is detected, as defined in ansi t1.403 and in tr-tsy-000194 or in the ds3 c-bit parity far-end alarm and control (feac) channel. the 64 th code ( 111111) is similar to the hdlc flag sequence and is used to indicate no valid code received. bit oriented codes are received on the facility data link channel or feac channel as a 16-bit sequence consisting of 8 ones, a zero, 6 code bits, and a trailing zero ( 111111110 xxxxxx0). bocs are validated w hen repeated at least 10 times. the receiver can be enabled to declare a received code valid if it has been observed for 8 out of 10 times or for 4 out of 5 times, as specified by the avc context bit. the code is declared removed if two code sequences
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 82 containing code values different from the detected code are received in a moving window of ten code periods. valid boc are indicated through the rboc interrupt status register. the boc bits are set to all ones ( 111111) if no valid c ode has been detected. an interrupt is generated to signal when a detected code has been validated, or optionally, when a valid code goes away (i.e. the boc bits go to all ones). 9.11 ds3/e3 hdlc receiver (rdlc) the rdlc is a microprocessor peripheral used to receive hdlc frames on the ds3 c-bit parity path maintenance data link, e3 g.832 network operator byte, e3 g.832 general purpose communications channel or e3 g.751 national use bit. the rdlc detects the change from flag characters to the first byte of data, removes stuffed zeros on the incoming data stream, receives packet data, and calculates the crc-ccitt frame check sequence (fcs). in the address matching mode, only those packets whose first data byte matches one of two programmable bytes or the universal address (all ones) are stored in the fifo. the two least significant bits of the address comparison can be masked for lapd sapi matching. received data is placed into a 128-byte fifo buffer. an interrupt is generated when a programmable number of bytes are stored in the fifo buffer. other sources of interrupt are detection of the terminating flag sequence, abort sequence, or fifo buffer overrun. the status register contains bits which indicate the overrun or empty fifo status, the interrupt status, and the occurrence of first flag or end of message bytes written into the fifo. the status register also indicates the abort, flag, and end of message status of the data just read from the fifo. on end of message, the status register indicates the fcs status and if the packet contained a non-integer number of bytes. 9.12 ds3/e3 performance monitor accumulator (ds3/e3-pmon) the performance monitor (pmon) block interfaces directly with the ds3 framer (ds3-frmr) and e3 framer. saturating counters are used to accumulate: ? line code violation (lcv) events ? parity error (perr) events
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 83 ? path parity error (cperr) events ? far end block error (febe) events ? excess zeros (exzs) ? framing bit error (ferr) events due to the off-line nature of the ds3 and e3 framers, pmon continues to accumulate performance metrics even while the framer has declared oof. when an accumulation interval is signaled by a write to the pmon register address space or to the global pmon update register, the pmon transfers the current counter values into microprocessor accessible holding registers and resets the counters to begin accumulating error events for the next interval. the counters are reset in such a manner that error events occurring during the reset period are not missed. when counter data is transferred into the holding registers, an interrupt is generated, providing the interrupt is enabled. if the holding registers have not been read since the last interrupt, an overrun status bit is set. in addition, a register is provided to indicate changes in the pmon counters since the last accumulation interval. whenever counter data is transferred into the holding registers, an interrupt is generated, providing the interrupt is enabled. if the holding registers have not been read since the last interrupt, an overrun status bit is set. 9.13 ds3 transmitter (ds3-tran) three ds3 transmitters are instantiated. each may be programmed to provide framing for unchannelized data from tdati[x] or the sbi bus, or framing for multiplexed t1s or e1s (itu-t rec. g.747). the ds3 transmitter (ds3-tran) block integrates circuitry required to insert the overhead bits into a ds3 bit stream and produce a b3zs-encoded signal. the t3-tran is directly compatible with the m23 and c-bit parity ds3 formats. status signals such as far end receive failure (ferf), the alarm indication signal, and the idle signal can be inserted when their transmission is enabled by internal register bits. ferf can also be automatically inserted on detection of any combination of los, oof or red, or ais by the ds3-frmr.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 84 a valid pair of p-bits is automatically calculated and inserted by the ds3-tran. when c-bit parity mode is selected, the path parity bits, and far end block error (febe) indications are automatically inserted. when enabled for c-bit parity operation, the feac channel is sourced by the bit- oriented code transmitter. the path maintenance data link messages are sourced by the tdpr data link transmitter. the ds3-tran supports diagnostic modes in which it inserts parity or path parity errors, f-bit framing errors, m-bit framing errors, invalid x or p-bits, line code violations, or all-zeros. 9.13.1 ds3 bit oriented code generation 63 of the possible 64 bit oriented codes may be transmitted in the ds3 c-bit parity far-end alarm and control (feac) channel. the 64 th code ( 111111) is similar to the hdlc flag sequence and is used to disable transmission of any bit oriented codes. when transmission is disabled the feac channel is set to all ones. bit oriented codes are transmitted on the ds3 far-end alarm and control channel as a 16-bit sequence consisting of 8 ones, a zero, 6 code bits, and a trailing zero ( 111111110 xxxxxx0) which is r epeated as long as the code is not 111111. the c ode to be transmitted is programmed by writing to the xboc code registers when it is held until the latest code has been transmitted at least 10 times. an interrupt or polling mechanism is used to determine when the most recent code written the xboc register is being transmitted and a new code can be accepted. 9.13.2 ds3 transmitter timing sources ds3 transmitter timing has three possible sources: 1. ticlk[3:1] input pins. if the system interface is sbi, then temap-84 is the sbi bus clock master, and uses the sajust_req output signal to issue timing justification requests to the link-layer device. if the system interface is serial clock and data, temap-84 derives tgapclk[3:1] from ticlk[3:1].) 2. integral ds3 clock synthesizer, which generates a gapped ds3 clock from the clk52m input pin, in response to sbi bus timing justification requests from the link-layer device. temap-84 is the sbi bus clock slave in this mode, and the sbi bus must be the system side option.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 85 external jitter attenuation is recommended when using this ds3 timing option. 3. recovered ds3 clock from the rclk[3:1] input pins. if the system interface is sbi, then temap-84 is the sbi bus clock master, as in case 1 above. if the system interface is serial clock and data, temap-84 derives tgapclk[3:1] from the recovered ds3 clock.) in each case, the ds3 transmitter drives the selected ds3 clock source onto the tclk output pins of the ds3/e3 line side interface. 9.14 ds3/e3 hdlc transmitters the hdlc transmitter provides a serial data link for the ds3 c-bit parity path maintenance data link, e3 g.832 network operator byte, e3 g.832 general purpose communications channel or e3 g.751 national use bit. the hdlc transmitter is used under microprocessor control to transmit hdlc data frames. it performs all of the data serialization, crc generation, zero-bit stuffing, as well as flag, and abort sequence insertion. upon completion of the message, a crc- ccitt frame check sequence (fcs) may be appended, followed by flags. if the hdlc transmitter data fifo underflows, an abort sequence is automatically transmitted. when enabled, the hdlc transmitter continuously transmits the flag sequence (01111110) until data is r eady to be transmitted. the default procedure provides automatic transmission of data once a complete packet is written. all complete packets of data will be transmitted. after the last data byte of a packet, the crc word (if crc insertion has been enabled) and a flag, or just a flag (if crc insertion has not been enabled) is transmitted. the hdlc transmitter then returns to the transmission of flag characters until the next packet is available for transmission. while working in this mode, the user must only be careful to avoid overfilling the fifo; underruns cannot occur unless the packet is greater than 128 bytes long. the hdlc transmitter will force transmission if the fifo is filled up regardless of whether or not the packet has been completely written into the fifo. a second mechanism transmits data when the fifo depth has reached a user configured upper threshold. the hdlc transmitter will continue to transmit data until the fifo depth has fallen below the upper threshold and the transmission of the last packet with data above the upper threshold has completed. in this mode, the user must be careful to avoid overruns and underruns. an interrupt can be generated once the fifo depth has fallen below a user configured lower threshold as an indicator for the user to write more data.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 86 interrupts can also be generated if the fifo underflows while transmitting a packet, when the fifo falls below a lower threshold, when the fifo is full, or if the fifo is overrun. if there are more than five consecutive ones in the raw transmit data or in the crc data, a zero is stuffed into the serial data output. this prevents the unintentional transmission of flag or abort sequences. abort characters can be continuously transmitted at any time by setting the abt bit. during packet transmission, an underrun situation can occur if data is not written before the previous byte has been depleted. in this case, an abort sequence is transmitted, and the controlling processor is notified via the udri interrupt. 9.15 ds3 pseudo random pattern generation and detection (prgd) the pseudo random pattern generator/detector (prgd) block is a software programmable test pattern generator, receiver, and analyzer for the ds3 payload. patterns may be generated in the transmit direction, and detected in the receive direction. two types of itu-t o.151 compliant test patterns are provided : pseudo-random and repetitive. the prgd can be programmed to generate any pseudo-random pattern with length up to 2 32 -1 bits or any user programmable bit pattern from 1 to 32 bits in length. in addition, the prgd can insert single bit errors or a bit error rate between 10 -1 to 10 -7 . the prgd can be programmed to check for the generated pseudo random pattern. the prgd can perform an auto synchronization to the expected pattern and accumulates the total number of bits received and the total number of bit errors in two 32-bit counters. the counters accumulate either over intervals defined by writes to the pattern detector registers or upon writes to the global pmon update register. when a transfer is triggered, the holding registers are updated, and the counters reset to begin accumulating for the next interval. the counters are reset in such a way that no events are missed. the data is then available in the holding registers until the next transfer. 9.16 m23 multiplexer (mx23) the m23 multiplexer (mx23) integrates circuitry required to asynchronously multiplex and demultiplex seven ds2 streams into, and out of, an m23 or c-bit parity formatted ds3 serial stream.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 87 when multiplexing seven ds2 streams into an m23 formatted ds3 stream, the mx23 function performs rate adaptation to the ds3 by integral fifo buffers. the c-bits are also generated and inserted. software control is provided to transmit ds2 ais and ds2 payload loopback requests. the loopback request is coded by inverting one of the three c-bits (the default option is compatible with ansi t1.107a section 8.2.1 and tr-tsy-000009 section 3.7). the mx23 also supports generation of a c-bit parity formatted ds3 stream by providing an internally generated ds2 rate clock corresponding to a 100% stuffing ratio. integrated m13 applications are supported by providing an internally generated ds2 rate clock corresponding to a 39.1% stuffing ratio. when demultiplexing seven ds2 streams from an m23 formatted ds3, the mx23 performs bit destuffing via interpretation of the c-bits. the mx23 also detects and indicates ds2 payload loopback requests encoded in the c-bits. as per ansi t1.107a section 8.2.1 and tr-tsy-000009 section 3.7, the loopback command is identified as c3 being the inverse of c1 and c2. because tr-tsy- 000233 section 5.3.14.1 recommends compatibility with non-compliant existing equipment, the two other loopback command possibilities are also supported. as per tr-tsy-000009 section 3.7, the loopback request must be present for five successive m-frames before declaration of detection. removal of the loopback request is declared when it has been absent for five successive m-frames. ds2 payload loopback can be activated or deactivated under software control. during payload loopback the ds2 stream being looped back still continues unaffected in the demultiplex direction to the ds2 framer. all seven demultiplexed ds2 streams can also be replaced with ais on an individual basis under register control or they can be configured to be replaced automatically on detection of out of frame, loss of signal, red alarm or alarm indication signal. 9.17 ds2 framer (ds2 frmr) the ds2 framer (ds2-frmr) integrates circuitry required for framing to a ds2 bit stream and is directly compatible with the m12 ds2 application. the ds2 frmr frames to a ds2 signal with a maximum average reframe time of less than 7 ms. both the f-bits and m-bits must be correct for a significant period of time before frame alignment is declared. once in frame, the ds2 frmr provides indications of the m-frame and m-subframe boundaries, and identifies the overhead bit positions in the incoming ds2 signal. depending on configuration, declaration of ds2 out-of-frame occurs when 2 out of 4 or 2 out of 5 consecutive f-bits are in error (these two ratios are recommended in tr-tsy-000009 section 4.1.2) or when one or more m-bit errors are detected in 3 out of 4 consecutive m-frames. the m-bit error criteria for oof can be disabled via the mbdis bit in the ds2 framer configuration
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 88 register. note that the ds2 framer is an off-line framer, indicating both oof and cofa. error events continue to be indicated even when the frmr is indicating oof, based on the previous frame alignment. the red alarm and alarm indication signal are detected by the ds2 frmr in 9.9 ms for ds2 format. the framer employs a simple integration algorithm (with a 1:1 slope) that is based on the occurrence of "valid" ds2 m-frame intervals. for the red alarm, a ds2 m-frame is said to be a "valid" interval if it contains a red defect, defined as the occurrence of an oof event during that m-frame. for ais, a ds2 m-frame is said to be a "valid" interval if it contains ais, defined as the occurrence of less than 9 zeros while the framer is out of frame during that m-frame. the discrepancy threshold ensures the detection algorithm operates in the presence of bit error rates of up to 10 -3 . each "valid" ds2 m- frame causes an integration counter to increment; "non-valid" ds2 m-frame intervals cause a decrement. red or ais is declared if the associated integrator count saturates at 53, resulting in a detection time of 9.9 ms. red or ais declaration is deasserted when the associated count decrements to 0. the ds2 x-bit is extracted by the ds2 frmr to provide an indication of far end receive failure. the ferf status is set to the current x/rai state only if the two successive x/rai bits were in the same state. the extracted ferf status is buffered for 6 ds2 m-frames before being reported within the ds2 frmr status register. this buffer ensures a virtually 100% probability of freezing the ferf status in a valid state during an out of frame occurrence. when an oof occurs, the ferf value is held at the state contained in the last buffer location corresponding to the previous sixth m-frame. this location is not updated until the oof condition is deasserted. meanwhile, the last four of the remaining five buffer locations are loaded with the frozen ferf state while the first buffer location corresponding to the current m-frame is continually updated every m- frame based on the above ferf definition. once correct frame alignment has been found and oof is deasserted, the first buffer location will contain a valid ferf status and the remaining five buffer locations are enabled to be updated every m-frame. ds2 m-bit and f-bit framing errors are indicated. these error indications are accumulated for performance monitoring purposes in internal, microprocessor readable counters. the performance monitoring accumulators continue to count error indications even while the framer is indicating oof. the ds2 frmr may be configured to generate interrupts on error events or status changes. all sources of interrupts can be masked or acknowledged via internal registers. internal registers are also used to configure the ds2 frmr.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 89 9.18 m12 multiplexer (mx12) the m12 multiplexer (mx12) integrates circuitry required to asynchronously multiplex and demultiplex four 1544 kbit/s streams into, and out of, an m12 formatted ds2 serial stream as defined in ansi t1.107 section 7. the m12 multiplexer also supports the itu-t rec. g.747 standard for the multiplexing of three 2048 kbit/s streams into a 6312 kbit/s stream. when multiplexing four ds1 streams into an m12 formatted ds2 stream, the mx12 function performs logical inversion on the second and fourth tributary streams. rate adaptation to the ds2 is performed by integral fifo buffers, controlled by timing circuitry. the fifo buffers accommodate in excess of 5.0 uipp of sinusoidal jitter on the ds1 clocks for all jitter frequencies. x, f, m, and c bits are also generated and inserted by the timing circuitry. software control is provided to transmit far end receive failure (ferf) indications, ds2 ais, and ds1 payload loopback requests. the loopback request is coded by inverting one of the three c-bits (the default option is compatible with ansi t1.107a section 8.2.1 and tr-tsy-000009 section 3.7).two diagnostic options are provided to invert the transmitted f or m bits. when demultiplexing four ds1 streams from an m12 formatted ds2, the mx12 performs bit destuffing via interpretation of the c-bits. the mx12 also detects and indicates ds1 payload loopback requests encoded in the c-bits. as per ansi t1.107 section 7.2.1.1 and tr-tsy-000009 section 3.7, the loopback command is identified as c3 being the inverse of c1 and c2. because tr-tsy- 000233 section 5.3.14.1 recommends compatibility with non-compliant existing equipment, the two other loopback command possibilities are also supported. as per tr-tsy-000009 section 3.7, the loopback request must be present for five successive m-frames before declaration of detection. removal of the loopback request is declared when it has been absent for five successive m-frames. ds1 payload loopback can be activated or deactivated under software control. during payload loopback the ds1 stream being looped back still continues unaffected in the demultiplex direction. the second and fourth demultiplexed ds1 streams are logically inverted. all four demultiplexed ds1 streams can be replaced with ais on an individual basis or can be configured for automatic replacement with ais on detection of out of frame or red alarm conditions. similar functionality is supplied for supporting itu-t recommendation g.747. software control is provided to transmit remote alarm indication (rai), 6312 kbit/s ais, and the reserved bit. a diagnostic option is provided to invert the transmitted frame alignment signal and parity bit. when demultiplexing three 2048 kbit/s streams from a g.747 formatted 6312 kbit/s stream, bit destuffing is performed via interpretation of the c-bits.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 90 tributary payload loopback can be activated or deactivated under software control. although no remote loopback request has been defined for g.747, inversion of the one of the c-bits, as selected by the loopback code select register, triggers a loopback request detection indication in anticipation of recommendation g.747 refinement. all three demultiplexed 2048 kbit/s streams can be replaced with ais on an individual basis. 9.19 e3 framer three instances of the e3 framer are independently programmed to frame to 34368 kbit/s frame formats. from each, the framed data is presented on rdato[x] or mapped into the sbi bus. the e3-frmr searches for frame alignment in the incoming serial stream based on either the g.751 or g.832 formats. for the g.751 format, the e3-frmr expects to see the selected framing pattern error-free for three consecutive frames before declaring frame alignment. for the g.832 format, the e3-frmr expects to see the selected framing pattern error-free for two consecutive frames before declaring frame alignment. once the frame alignment is established, the incoming data is continuously monitored for framing bit errors and byte interleaved parity errors (in g.832 format). while in-frame, the e3-frmr also extracts various overhead bytes and processes them according to the framing format selected: in g.832 e3 format, the e3-frmr extracts: ? the trail trace bytes; ? the ferf bit and indicates an alarm when the ferf bit is a logic 1 for 3 or 5 consecutive frames. the ferf indication is removed when the ferf bit is a logic 0 for 3 or 5 consecutive frames; ? the febe bit for accumulation in pmon; ? the payload type bits and buffers them so that they can be read by the microprocessor; ? the timing marker bit and asserts the timing marker indication when the value of the extracted bit has been in the same state for 3 or 5 consecutive frames; ? the network operator byte for processing by the hdlc receiver when the rnetop bit in the e3 data link control register is logic 1;
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 91 ? the general purpose communication channel byte for processing by the hdlc receiver when the rnetop bit in the e3 data link control register is logic 0. in g.751 e3 mode, the e3-frmr extracts: ? the remote alarm indication bit (bit 11 of the frame) and indicates a remote alarm when the rai bit is a logic 1 for 3 or 5 consecutive frames. similarly, the remote alarm is removed when the rai bit is logic 0 for 3 or 5 consecutive frames; ? the national use reserved bit (bit 12 of the frame) for further processing in the hdlc receiver when the rnetop bit in the e3 data link control register is logic 0. optionally, an interrupt can be generated when the national use bit changes state. the e3-frmr declares out of frame alignment if the framing pattern is in error for four consecutive frames. the e3-frmr is an "off-line" framer, where all frame alignment indications, all overhead bit indications, and all overhead bit processing continue based on the previous alignment. once the framer has determined the new frame alignment, the out-of-frame indication is removed and a cofa indication is declared if the new alignment differs from the previous alignment. the e3-frmr detects the presence of ais in the incoming data stream when less than 8 zeros in a frame are detected while the framer is oof in g.832 mode, or when less than 5 zeros in a frame are detected while oof in g.751 mode. this algorithm provides a probability of detecting ais within a single frame in the presence of a 10 -3 ber as 92.9% in g.832 and 98.0% in g.751. after five frames, the probability of detection rises to >99.999% for both formats. loss of signal is los is declared when no marks have been received for 32 consecutive bit periods. loss of signal is de-asserted after 32 bit periods during which there is no sequence of four consecutive zeros. e3 loss of frame detection is provided as recommended by itu-t g.783 with programmable integration periods of 1ms, 2ms, or 3ms. while integrating up to assert lof, the counter will integrate up when the framer asserts an out of frame condition and integrates down when the framer de-asserts the out of frame condition. once an lof is asserted, the framer must not assert oof for the entire integration period before lof is de-asserted. the e3-frmr can also be enabled to automatically assert the rai/ferf indication in the outgoing transmit stream upon detection of any combination of
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 92 los, oof or ais. the e3-frmr can also be enabled to automatically insert g.832 febe upon detection of receive bip-8 errors. 9.20 e3 transmitter three e3 transmitters provide framing insertion for 34368 kbit/s unchannelized data from tdati[3:1] or the sbi bus. the e3 transmitter (e3-tran) block integrates circuitry required to insert the overhead bits into an e3 bit stream and produce an hdb3-encoded signal. the e3-tran is directly compatible with the g.751 and g.832 framing formats. the e3-tran generates the frame alignment signal and inserts it into the incoming serial stream based on either the g.751 or g.832 formats. all overhead and status bits in each frame format can be individually controlled by register bits. while in certain framing format modes, the e3-tran generates various overhead bytes according to the following: in g.832 e3 format, the e3-tran: ? inserts the bip-8 byte calculated over the preceding frame; ? inserts the trail trace bytes; ? inserts the ferf bit via a register bit or, optionally, when the e3-frmr declares oof, or when the loss of cell delineation (lcd) defect is declared; ? inserts the febe bit, which is set to logic 1 when one or more bip-8 errors are detected by the receive framer. if there are no bip-8 errors indicated by the e3-frmr, the e3-tran sets the febe bit to logic 0; ? inserts the payload type bits based on the register value set by the microprocessor; ? inserts the tributary unit multiframe indicator bits either via the toh overhead stream or by register bit values set by the microprocessor; ? inserts the timing marker bit via a register bit; ? inserts the network operator (nr) byte from the tdpr block when the tnetop bit in the e3 data link control register is logic 1; otherwise, the nr byte is set to all ones. all 8 bits of the network operator byte are available for use as a datalink;
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 93 ? inserts the general purpose communication channel (gc) byte from the tdpr block when the tnetop bit in the e3 data link control register is logic 0; otherwise, the byte is set to all ones. in g.751 e3 mode, the e3-tran : ? inserts the remote alarm indication bit (bit 11 of the frame) either via a register bit or, optionally, when the e3-frmr declares oof; ? inserts the national use reserved bit (bit 12 of the frame) either as a fixed value through a register bit or from the hdlc transmitter as configured by the tnetop bit in the e3 data link control register and the natuse bit in the e3 tran configuration register; ? optionally identifies the tributary justification bits and stuff opportunity bits as either overhead or payload for payload mappings that take advantage of the full bandwidth. further, the e3-tran can provide insertion of bit errors in the framing pattern or in the parity bits, and insertion of single line code violations for diagnostic purposes. 9.20.1 e3 transmitter timing sources e3 transmitter timing has three possible sources: 1. ticlk[3:1] input pins. if the system interface is sbi, then temap-84 is the sbi bus clock master, and uses the sajust_req output signal to issue timing justification requests to the link-layer device. if the system interface is serial clock and data, temap-84 derives tgapclk[3:1] from ticlk[3:1].) 2. integral e3 clock synthesizer, which generates a gapped e3 clock from the clk52m input pin, in response to sbi bus timing justification requests from the link-layer device. temap-84 is the sbi bus clock slave in this mode, and the sbi bus must be the system side option. external jitter attenuation is recommended when using this e3 timing option. 3. recovered e3 clock from the rclk[3:1] input pins. if the system interface is sbi, then temap-84 is the sbi bus clock master, as in case 1 above. if the system interface is serial clock and data, temap-84 derives tgapclk[3:1] from the recovered e3 clock.)
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 94 in each case, the e3 transmitter drives the selected e3 clock source onto the tclk output pins of the ds3/e3 line side interface. 9.21 e3 trail trace buffer the trail trace buffer (ttb) extracts and sources the trail trace message carried in the tr byte of the g.832 e3 stream. the message is used by the os (operating system) to prevent delivery of traffic from the wrong source and is 16 bytes in length. the 16-byte message is framed by the pti multiframe alignment signal (tmfas = 'b10000000 00000000). one bit of the tmfas is placed in the most significant bit of each message byte. in the receive direction, the extracted message is stored in the internal ram for review by an external microprocessor. by default, the byte of a 16-byte message with its most significant bit set high will be written to the first location in the ram. the extracted trail trace message is checked for consistency between consecutive multiframes. a message received unchanged three or five times (programmable) is accepted for comparison with the copy previously written into the internal ram by the external microprocessor. alarms are raised to indicate reception of unstable and mismatched messages. in the transmit direction, the trail trace message is sourced from the internal ram for insertion into the tr byte by the e3-tran. the payload type label carried in the ma byte of the g.832 e3 stream is also extracted. the label is used to ensure that the adaptation function at the trail termination sink is compatible with the adaptation function at the trail termination source. the payload type label is check for consistency between consecutive multiframes. a payload type label received unchanged for five frames is accepted for comparison with the copy previously written into the ttb by the external microprocessor. alarms are raised to indicate reception of unstable and mismatched payload type label bits. 9.22 tributary payload processor (vtpp) each of of three tributary payload processors (vtpp) processes the virtual tributaries within an sts-1, au3, or tug3. the vtpp can be configured to process either vt1.5s or vt2s within an sts-1 or either tu11s or tu12s within an au3 or tug3. the number of tributaries managed by each vtpp ranges from 21 (when configured to process all vt2s or equivalently all tu12s) to 28 (when configured to process all vt1.5s or equivalently all tu11s). the tributary payload processor is used in both the ingress and egress data paths. in the egress direction the pointer interpreter section of the vtpp can be bypassed on a per tributary basis to allow for pointer generator in the absence of valid pointers which is necessary when mapping floating transparent virtual tributaries from the sbi bus.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 95 9.22.1 incoming multiframe detector the multiframe alignment sequence in the path overhead h4 byte is monitored for the bit patterns of 00, 01, 10, 11 in the two least significant bits. if an unexpected value is detected, the primary multiframe will be kept, and a second multiframe process will, in parallel, check for a phase shift. the primary process will enter out of multiframe state (oom). a new multiframe alignment is chosen, and oom state is exited when four consecutive correct multiframe patterns are detected. loss of multiframe (lom) is declared after residing in the oom state at the ninth h4 byte without re-alignment. in counting to nine, the out of sequence h4 byte that triggered the transition to the oom state is counted as the first. a new multiframe alignment is chosen, and lom state is exited when four consecutive correct multiframe patterns are detected. changes in multiframe alignments are detected and reported. 9.22.2 pointer interpreter the pointer interpreter is a time-sliced state machine that can process up to 28 independent tributaries. the state vector is saved in ram as directed by the incoming timing generator. the pointer interpreter processes the incoming tributary pointers such that all bytes within the tributary synchronous payload envelope can be identified and written into the unique payload first-in first-out buffer for the tributary in question. a marker that tags the v5 byte is passed through the payload buffer. the incoming timing generator directs the pointer interpreter to the correct payload buffer for the tributary being processed. the pointer interpreter processes the incoming pointers (v1/v2) as specified in the references. the pointer value is used to determine the location of the tributary path overhead byte (v5) in the incoming tug3 or sts-1 (au3) stream. 9.22.3 payload buffer the payload buffer is a bank of fifo buffers. it is synchronous in operation and is based on a time-sliced ram. the three 19.44 mhz clock cycles in each 6.48 mhz period are shared between the read and write operations. the pointer interpreter writes tributary payload data and the v5 tag into the payload buffer. a 16 byte fifo buffer is provided for each of the (up to 28) tributaries. address information is also passed through the payload buffer to allow fifo fill status to be determined by the pointer generator.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 96 9.22.4 pointer generator 1. the pointer generator block generates the tributary pointers (v1/v2) as specified in the references. the pointer value is used to determine the location of the tributary path overhead byte (v5) on the outgoing stream. the pointer generator is a time-sliced state machine that can process up to 28 independent tributaries. the state vector is saved in ram at the address associated with the current tributary. the pointer generator fills the outgoing tributary synchronous payload envelopes with bytes read from the associated fifo in the payload buffer for the current tributary. the pointer generator creates pointers in the v1-v3 bytes of the outgoing data stream. the marker that tags the v5 byte that is passed through the payload buffer is used to align the pointer. the outgoing timing generator directs the pointer generator to the fifo in the payload buffer that is associated with the tributary being processed. the pointer generator monitors the fill levels of the payload buffers and inserts outgoing pointer justifications as necessary to avoid fifo spillage. normally, the pointer generator has a fifo dead band of two bytes. the dead band can be collapse to one so that any incoming pointer justifications will be reflected by a corresponding outgoing justification with no attenuation. signals are output by the pointer generator that identify outgoing v5 bytes and the tributary synchronous payload envelopes. on a per tributary basis, tributary path ais and tributary idle (unequipped) can be inserted as controlled by microprocessor accessible registers. the idle code is selectable globally for the entire vc3 or tug3 to be all-zeros or all-ones. it is also possible to force an inverted new data flag on individual tributaries for the purpose of diagnosing downstream pointer processors. tributary path ais is automatically inserted into outgoing tributaries if the pointer interpreter detects tributary path ais on the corresponding incoming tributary. 9.23 receive tributary path overhead processor (rtop) each one of three tributary path overhead processors (rtop) monitors the outgoing stream of the tributary payload processor (vtpp) and processes the tributaries within an sts-1, au3, or tug3. the rtop can be configured to process all the vt1.5s or vt2s that can be carried in an sts-1 or all the tu11s or tu12s that can be carried in an au3 or tug3. the number of tributaries managed by each rtop ranges from 21 (when configured to process all vt2s or all tu12s) to 28 (when configured to process all vt1.5s or all tu11s). the rtop provides tributary performance monitoring of incoming tributaries. bit interleaved parity of the incoming tributaries is computed and compared with the bip-2 code encoded in the v5 byte of the tributary. errors between the computed and received values are accumulated. rtop also accumulates far
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 97 end block error codes. incoming path signal label is debounced and compared with the provisioned value. path signal label unstable, path signal label mismatch and change of path signal label event are identified. 9.23.1 error monitor the error monitor block contains a set of 12-bit counters that are used to accumulate tributary path bip-2 errors, and a set of 11-bit counters to accumulate far end block errors (febe). the contents of the counters may be transferred to a holding ram, and the counters reset under microprocessor control. tributary path bip-2 errors are detected by comparing the tributary path bip-2 bits in the v5 byte extracted from the current multiframe, to the bip-2 value computed for the previous multiframe. bip-2 errors may be accumulated on a block or nibble basis as controlled by software configurable registers. far end block errors (febes) are detected by extracting the febe bit from the tributary path overhead byte (v5). tributary path remote defect indication (rdi) and remote failure indication (rfi) are detected by extracting bit 8 and bit 4 respectively of the tributary path overhead byte (v5). the rdi is recognized when bit 8 of the v5 byte is set high for five or ten consecutive multiframes while rfi is recognized when bit 4 of v5 is set high for five or ten consecutive frames. the rdi and rfi bits may be treated as a two-bit code word. a code change is only recognized when the code is unchanged for five or ten frames. the tributary path signal label (psl) found in the tributary path overhead byte (v5) is processed. an incoming psl is accepted when it is received unchanged for five consecutive multiframes. the accepted psl is compared with the associated provisioned value. the psl match/mismatch state is determined by the following: table 2 - path signal label mismatch state expected psl accepted psl pslm state 000 000 match 000 001 mismatch 000 pdi code mismatch 000 xxx 000, 001, pdi code mismatch
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 98 expected psl accepted psl pslm state 001 000 mismatch 001 001 match 001 pdi code match 001 xxx 000, 001, pdi code match pdi code 000 mismatch pdi code 001 match pdi code pdi code match pdi code xxx 000, 001, pdi code mismatch xxx 000, 001, pdi code 000 mismatch xxx 000, 001, pdi code 001 match xxx 000, 001, pdi code xxx match xxx 000, 001, pdi code yyy mismatch each time an incoming psl differs from the one in the previous multiframe, the psl unstable counter is incremented. thus, a single bit error in the psl in a sequence of constant psl values will cause the counter to increment twice, once on the errored psl and again on the first error-free psl. the incoming psl is considered unstable when the counter reaches five. the counter is cleared when the same psl is received for five consecutive multiframes. 9.24 receive tributary trace buffer (rttb) when configured for sonet compatible operation, each one of three receive tributary trace buffers (rttb) processes the tributary trace message of all the tributaries in an sts-1 stream. each of the seven tributary groups (vt groups) may be independently configured to accept any of the four tributary types (vt1.5, vt2, vt3, and vt6). the rttb extracts tributary trace message from each tributary and stores it in one of a set of internal buffers. the rttb may be configured for sdh compatible operation. the incoming stream may carry an au3 of an stm1 stream or a tug3 in an au4 of an stm1 stream.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 99 the tributary trace message of each tributary is extracted form the j2 (j1 in tu3 mode) byte. it is written to the internal buffer corresponding to the tributary. the internal buffer may behave as a simple circular buffer, or optionally, be synchronized to the framing pattern embedded in the message. for a 16-byte trail trace identifier, the first byte is identified by a logic one in the most significant bit. for a 64-byte tributary trace message, the last two bytes are set to the ascii characters for carriage-return (cr) and linefeed (lf). an extracted message is declared the accepted message, if it is received unchanged for 3 multiframes. the accepted message is compared with the locally provisioned expected message. a tributary trace identifier mismatch alarm (tim) is asserted when the accepted and expected messages differ. conversely, tim is negated when the messages are identical. an interrupt is optionally generated upon a change in the tim state. messages of all-zeros bytes cannot become accepted and, therefore, have no effect on the tim state. the rttb also monitors for tributary trace unstable conditions. each time a tributary trace message that is received differs from the previous message, the unstable counter is incremented by one. the tributary trace unstable alarm (tiu) is asserted when the unstable counter reaches eight. the unstable counter is cleared and the unstable alarm negated when the extracted message remains unchanged for enough multiframes to meet the acceptance criteria. an interrupt is optionally generated upon a change in the tiu state. 9.25 receive tributary bit asynchronous demapper (rtdm) each one of three receive tributary demappers (rtdm) demaps up to 28 t1 or 21 e1 bit asynchronous mapped signals from an sts-1 spe, tug3 within a stm-1/vc4 or stm-1 vc3 payload. the bit asynchronous t1 mapping consists of 104 octets every 500 s (2 khz) and is shown in table 3. the bit asynchronous e1 mapping consists of 140 octets every 500us and is shown in table 4.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 100 table 3 - asynchronous t1 tributary mapping v5 rrrrrrir 24 bytes - 8i j2 c 1 c 2 ooooir 24 bytes - 8i z6 c 1 c 2 ooooir 24 bytes - 8i z7 c 1 c 2 rrrs 1 s 2 r 24 bytes - 8i r: fixed stuff bit - set to logic ?0? or ?1? c: stuff control bit - set to logic ?1? for stuff indication s: stuff opportunity bit - when stuff control bit is ?0?, stuff opportunity is i bit o: overhead i: t1 payload information
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 101 table 4 - asynchronous e1 tributary mapping v5 r 32 bytes - 8i r j2 c 1 c 2 oooorr 32 bytes ? 8i r z6 c 1 c 2 oooorr 32 bytes ? 8i r z7 c 1 c 2 rrrrrs 1 s 2 i i i i i i i 31 bytes ? 8i r r: fixed stuff bit - set to logic ?0? or ?1? c: stuff control bit - set to logic ?1? for stuff indication s: stuff opportunity bit - when stuff control bit is ?0?, stuff opportunity is i bit o: overhead i: e1 payload information the rtdm buffers the tributary synchronous payload envelope bytes of the incoming tributaries in individual fifos to accommodate tributary pointer justifications. the rtdm performs majority voting on the tributary stuff control (c1, c2) bits. if the majority of each set of the stuff control bits indicate a stuff operation, then the associated stuff opportunity bit (s1, s2) will not carry t1 or e1 payload.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 102 conversely, if the majority of the stuff control bits indicate a data operation, the appropriate stuff opportunity bit(s) will carry t1 or e1 payload. the rtdm, in cooperation with the t1/e1 jitter attenuator, attenuates jitter introduced by pointer justification events. the t1/e1 jitter attenuator may be bypassed, in which case an external device may use the sbi link rate octet generated by rtdm to determine the clock phase. when a pointer justification is detected, the rtdm issues evenly spaced 1/12 ui t1 adjustments or 1/9 ui e1 adjustments encoded in the sbi link rate octet. the rtdm optionally acts as a time switch. when time switching is enabled, the association of timeslots on the system interface (sbi or h-mvip) to incoming tributaries is software configurable. there are two pages in the time switch configuration ram. one page is software selectable to be the active page and the other the stand-by page. the configuration in the active page is used to switch incoming tributaries. the stand-by page can be programmed to the next switch configuration. change of page selection is effected immediately. the one constraint on switch configuration is that the all the remapped tributaries in an spe must be of the same type (t1 or e1). 9.26 receive tributary byte synchronous demapper each one of three receive tributary byte synchronous demappers demaps up to 28 t1 or 21 e1 byte synchronous mapped signals from an sts-1 spe, tug3 within a stm-1/vc4 or stm-1 vc3 payload. the demapping is done inaccordance with itu-t recommendation g.709 and ansi t1.105. byte synchronous demapping is enabled on a per-tributary basis by setting the enbl bit through the byte synchronous demapping tributary control ram indirect access data register and by bypassing the receive jitter attenuator by setting the rjatbyp bit through the rjat indirect channel data register. given that frame alignment is provided by the mapping function, the t1/e1 framer doesn?t provide the frame alignment for the system interface. if the tributary ?f? bit position contains valid framing information, the t1/e1 framer may be used for performance and alarm monitoring. signaling, if present, may be dealt with in two ways for t1. by default, the t1 framer attempts to find frame and extracts the signaling from the robbed bit signaling positions. alternately, the values encoded in the s 1 s 2 s 3 s 4 bit positions are presented on the system interface verbatim without debounce or freezing if the rawsig bit programmed through the sigx indirect channel data registers is logic 1. this is programmed on a per-tributary basis. for e1, the signaling is extracted from ?multiframe alignment signal? byte.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 103 9.27 ds3 mapper drop side (d3md) each one of three ds3 mapper drop side (d3md) blocks demaps a ds3 signal from an sts-1 (stm-0/au3) payload. the demapped ds3 is presented to the ds3 framer and subsequently presented on rdat[x]. optionally, it is mapped into the sbi bus or demultiplexed into 28 ds1s or 21 e1s. the asynchronous ds3 mapping consists of 9 rows every 125 s (8 khz). each row contains 621 information bits, 5 stuff control bits, 1 stuff opportunity bit, and 2 overhead communication channel bits. fixed stuff bytes are used to fill the remaining bytes. the asynchronous ds3 mapping is shown in table 5. table 5 - asynchronous ds3 mapping to sts-1 (stm-0/au3) j1 2 x 8r rrciiiii 25 x 8i 2 x 8r ccrrrrrr 26 x 8i 2 x 8r ccrroors 26 x 8i 2 x 8r rrciiiii 25 x 8i 2 x 8r ccrrrrrr 26 x 8i 2 x 8r ccrroors 26 x 8i 2 x 8r rrciiiii 25 x 8i 2 x 8r ccrrrrrr 26 x 8i 2 x 8r ccrroors 26 x 8i sts 2 x 8r rrciiiii 25 x 8i 2 x 8r ccrrrrrr 26 x 8i 2 x 8r ccrroors 26 x 8i poh 2 x 8r rrciiiii 25 x 8i 2 x 8r ccrrrrrr 26 x 8i 2 x 8r ccrroors 26 x 8i 2 x 8r rrciiiii 25 x 8i 2 x 8r ccrrrrrr 26 x 8i 2 x 8r ccrroors 26 x 8i 2 x 8r rrciiiii 25 x 8i 2 x 8r ccrrrrrr 26 x 8i 2 x 8r ccrroors 26 x 8i 2 x 8r rrciiiii 25 x 8i 2 x 8r ccrrrrrr 26 x 8i 2 x 8r ccrroors 26 x 8i 2 x 8r rrciiiii 25 x 8i 2 x 8r ccrrrrrr 26 x 8i 2 x 8r ccrroors 26 x 8i r: fixed stuff bit - set to logic ?0? or ?1? c: stuff control bit - set to logic ?1? for stuff indication s: stuff opportunity bit - when stuff control bit is ?0?, stuff opportunity is i bit o: overhead communication channel i: ds3 payload information 9.27.1 ds3 demapper the d3md performs majority vote on the received c-bits. if 3 out of 5 c-bits are ?1?s, the associated s bit is interpreted as a stuff bit. if 3 out of 5 c-bits are ?0?s, the associated s bit is interpreted as an information bit. the information bits are written to an elastic store and the fixed stuff bits (r) are ignored.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 104 given a path signal label mismatch (pslm) or path signal label unstable (pslu), the d3md ignores the sts-1 (stm-0/au3) spe and writes a ds3 ais pattern to the elastic store. in addition, the desynchronization algorithm assumes a nominal ratio of data to stuff bits carried in the s bits (1 out of 3 s bits is assumed to be an information (data) bit). ds3 ais is shown in table 6. table 6 - ds3 ais format. x (1) d f (1) d c (0) d f (0) d c (0) d f (0) d c (0) d f (1) d x (1) d f (1) d c (0) d f (0) d c (0) d f (0) d c (0) d f (1) d p (p) d f (1) d c (0) d f (0) d c (0) d f (0) d c (0) d f (1) d p (p) d f (1) d c (0) d f (0) d c (0) d f (0) d c (0) d f (1) d m (0) d f (1) d c (0) d f (0) d c (0) d f (0) d c (0) d f (1) d m (1) d f (1) d c (0) d f (0) d c (0) d f (0) d c (0) d f (1) d m (0) d f (1) d c (0) d f (0) d c (0) d f (0) d c (0) d f (1) d ? valid m-frame alignment bits (m-bits), m-subframe alignment bits (f-bits), and parity bit of the preceding m-frame (p-bits). the two p-bits are identical, either both are zeros or ones. ? all the c-bits in the m-frame are set to zeros ? the x-bits are set to ones ? the information bit (84 data bits with repeating sequence of 1010..) 9.27.2 ds3 demapper elastic store the elastic store block is provided to compensate for frequency differences between the ds-3 stream extracted from the sts-1 (stm-0/au3) spe and the clk52m clock input. the ds3 demapper extracts i bits from the sts-1 (stm-0/au3) spe and writes the bits into a 128 bit (16 byte) elastic store. eight bytes are provided for sonet/sdh overhead (3 bytes for toh, 1 byte for a positive stuff, 1 byte for poh) and ds3 reserve stuffing bits (2 bytes for r bits, and 3 overhead bits which is rounded-up to 1 byte). the remaining 8 bytes are provided for path pointer adjustments. data is read out of the elastic store using a divide by 8 version of the input clk52m clock. if an overflow or underflow condition occurs, an interrupt is
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 105 optionally asserted and the elastic store read and write address are reset to the startup values (logically 180 degrees apart). 9.27.3 ds3 desynchronizer the desynchronizer monitors the elastic store level to control the de-stuffing algorithm to avoid overflow and underflow conditions. the desynchronizer assumes either a 51.84 mhz clock or a 44.928 mhz clock (provided via input clk52m). when using a 44.928 mhz clk52m clock, the ds3 clock is generated using a fixed 8 khz interval. the 8khz interval is subdivided into 9 rows. each row contains either 621 or 622 clock periods. the clk52m contains 624 cycles per row. to generate 621 pulses, a gap pattern of 207 clocks + 1 clock gap + 207 clocks + 1 clock gap + 207 clocks + 1 clock gap is used. to generate 622 pulses, a gap pattern of 207 clocks + 1 clock gap + 207 clocks + 1 clock gap + 208 clocks is used. when using a 51.84 mhz clk52m clock, the ds3 clock is generated using similar gapping patterns. to generate 621 pulses per row, a gapping pattern of 63 * (7 clocks + 1 clock gap) + 36 * (5 clocks + 1 clock gap) is used. to generate 622 pulses per row, a gapping pattern of 63 * (7 clocks + 1 clock gap) + 35 * (5 clocks + 1 clock gap) + 6 clocks) is used. table 7 illustrates the gap patterns used to generate the desynchronized ds3 clock under the normal, ds3 ais, faster and slower status. the faster pattern is used to drain the elastic store to avoid overflows. the slower pattern is used to allow the elastic store to fill to avoid underflows.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 106 table 7 - ds3 desynchronizer clock gapping algorithm. row number normal or ds3 ais run faster run slower 1 621 621 621 2 621 621 621 3 622 622 622 4 621 621 621 5 621 622 621 6 622 622 621 7 621 621 621 8 621 622 621 9 622 622 621 9.28 transmit tributary path overhead processor (ttop) each one of three transmit tributary path overhead processors (ttop) generates the path overhead for up to 28 vt1.5/tu-11s or 21 vt2/tu-12s. when configured for sonet compatible operation, the ttop inserts the four tributary path overhead bytes (v5, j2, z6, and z7) to each tributary. the ttop may also be configured for sdh compatible operation. the incoming stm-1 stream may carry three au3s or an au4 with three tug3s. the ttop computes the bip-2 code in the current tributary spe and inserts the result into the bip-2 bits of the v5 byte in the next tributary spe. the tributary path signal label in the v5 byte of each tributary can be sourced from internal registers. the tributary far end block error bit in the v5 byte of each tributary is inserted based of the bip error count detected at a companion rtop block. the tributary remote failure indication and remote defect indication bits in the v5 or the z7 byte of each tributary is inserted based on the tributary alarm status of the companion rtop tsb. the ttop inserts the tributary trail trace identifier (tti) into the j2 byte. each tributary is provided with a 64-byte buffer to store the identifier. to transmit a 16- byte message, one must write four identical copies to the buffer. one shadow buffer is available for temporary replacement of a selected transmitted tti while the 64-byte identifier buffer is being updated. data is retrieved sequentially from the active buffer at each j2 byte position. no crc insertion is performed; any crc must be written into the trail trace buffer. the shadow buffer can be programmed with new messages without timing constraints when inactive. an
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 107 inactive 64-byte identifier buffer can also be programmed with new messages without timing constraints. programming for tti buffers is done one buffer at a time by first programming the shadow buffer, switching to the shadow buffer for the desired tributary, updating the desired tributary identifier buffer and finally switching back from the shadow buffer to the tributary buffer. switching between the shadow buffer and normal buffer is synchronized to the start of each identifier on a per-tributary basis. 9.29 transmit remote alarm processor (trap) when configured for sonet compatible operation, each one of three trap sonet/sdh transmit remote alarm processors processes remote alarm indications of tributaries in an sts-3 stream. the virtual tributaries within an sts-1 stream may be configured to accept either vt1.5 or vt2 tributary types. the trap may also be configured for sdh compatible operation. the incoming stm-1 stream may carry three au3s or an au4 with three tug3s. two methods of encoding tributary remote alarms are supported, as selected on a per-tributary basis by the erdi bits of the trap control registers and ttop control registers. if the erdi bits for a tributary are logic 0, rdi-v is transmitted by setting bit 8 of the v5 byte to logic 1 and rfi-v is transmitted by setting bit 4 of the v5 byte to logic 1. bits 6 and 7 of the z7 will be zeros. if the erdi bits for a tributary are logic 1, extended rdi is effected. the triggers for erdi-v are programmable, but the following is always true if erdi is configured: - bit 8 of the v5 byte equals bit 5 of the z7 byte, - bit 7 of the z7 byte is always the complement of bit 6 of the z7 byte, and - if byte synchronous mapping is being used, bit 4 of v5 will equal the value programmed through the byte synchronous mapping tributary control indirect access data register; otherwise, it will be logic 0. if the forceen bit of the trap control register is logic 1 then bit 8 of v5 (plus bit 5 of z7 if erdi) reflects the state of the rdi bit of the trap control register and the ardi bit of the trap control register sets bit 6 of z7 if erdi; otherwise it sets bit 4 of v5. if forceen is logic 0, the source for rdi-v and rfi-v can be any one of the radeast input, the radwest input or telecom drop bus alarms. the trap may be configured to insert tributary remote defect indications (rdi-v), tributary remote fault indications (rfi-v) and tributary remote error indications (rei-v) based on alarms detected in tributaries received on the telecom drop bus, lddata[7:0]. the contents of the sonet/sdh master tributary remote defect indication control register determine which alarms
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 108 affect the state of bit 8 of v5 and (if erdi is set) bit 5 of z7. the contents of the sonet/sdh master tributary auxiliary remote defect indication control register determine the which alarms affect the state of bit 4 of v5 if not erdi or bit 6 of z7 if erdi. alternatively, the trap may also be configured to extract rdi-v, rfi-v and rei- v from two independent serial remote alarm ports, radeast and radwest. in all cases, the rdi-v and rfi-v state will be sent for a minimum of 10 multiframes before changing, unless a higher priority alarm is required. the trap provides selection between the telecom drop bus alarms and the two remote serial alarm ports for the source of remote alarm status on a per-tributary basis. by default, all three sources are disabled. tributaries in any of the three sources of remote alarms can be mapped to arbitrary tributaries in the outgoing data stream. the mapping is configured through the trap indirect remote alarm page address, trap indirect remote alarm tributary address and trap indirect datapath tributary data registers. a valid tu designation written via the trap indirect datapath tributary data register is all that is required to enable the alarms for the outgoing tributary specified by the trap indirect remote alarm tributary address register. although it is possible to have any subset of the three sources enabled, it is usual to have only one of the three sources enabled for a particular tributary. 9.30 transmit tributary bit asynchronous mapper (ttmp) each one of three transmit tributary mapper blocks bit asynchronously maps up to 28 t1 or 21 e1 streams into an sts-1 spe, tug3 in a stm-1/vc4 or stm- 1/vc3 payload. the ttmp compensates for any frequency differences between the incoming individual serial bit rates and the available sts-1 or stm-1/vc3 payload capacity. the asynchronous t1 mapping consists of 104 octets every 500 s (2 khz). the asynchronous e1 mapping consists of 140 octets every 500 s (2 khz). refer to the rtdm block for a description of the asynchronous t1 and e1 mappings. the tributary mapper is a time-sliced state machine which uses a payload buffer as an elastic store. the t1 or e1 streams are read from the payload buffer, and mapped into vt1.5 payloads and vt2 payloads using bit asynchronous mapping only. the tributary mapper compensates for phase and frequency offsets using bit stuffing. a jitter-reducing control loop is used to monitor the payload buffer depth and reduce mapping jitter to 1.0 ui. to reduce mapping jitter even further, a dither technique is inserted between the control loop and the stuff bit generator resulting in an acceptable desynchronizer mapping jitter of about 0.3 ui.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 109 the tributary mapper may optionally act as a time switch. when time switch enable is active, the association of tributary mapper vt payloads to logical fifo data streams is software configurable. there are two pages in the time switch configuration ram. one page is software selectable to be the active page and the other the stand-by page. the configuration in the active page is used to associate outgoing vt payloads to logical fifos. the stand-by page can be programmed to the next switch configuration. change of page selection is synchronized to incoming stream frame boundaries. when time switch enable is inactive, the association of outgoing vt payloads to logical fifos is fixed. the ttmp outputs the sts-1, tug3 in a stm-1/vc4 or stm-1/vc3 with the bit asynchronous mapped t1s or e1s onto an internal bus for further processing by the transmit tributary payload processor block. 9.31 transmit tributary byte synchronous mapper each one of three transmit tributary mapper blocks byte synchronously maps up to 28 t1 or 21 e1 streams into an sts-1 spe, tug3 in a stm-1/vc4 or stm-1/vc3 payload. the mapping is done inaccordance with itu-t recommendation g.709 and ansi t1.105. byte synchronous mapping is enabled on a per-tributary basis by setting the enbl bit through the byte synchronous mapping tributary control ram indirect access data register, by bypassing the transmit jitter attenuator by setting the tjatbyp bit through thetjat indirect channel data register and by disabling the egress vtpp pointer interpretation via the eptrbyp or etvtptrdis bits. by default the t1/e1 framer inserts valid framing into the t1 ?f? bit and e1 ts0. the t1 signaling received from the system interface is encoded into the s 1 s 2 s 3 s 4 bit positions. signaling is also inserted into the robbed bit signaling positions as enabled by the sigc bits programmed through the tpcc indirect channel data registers. for e1, the signaling insertion is independent of the mapping. 9.32 ds3 mapper add side (d3ma) each one of three ds3 mapper add side (d3ma) blocks maps a ds3 signal into an sts-1 (stm-0/au3) payload and compensate for any frequency differences between the incoming ds3 serial bit rate (ticlk) and the available sts-1 (stm-0/au3) spe mapped payload capacity. the asynchronous ds3 mapping consists of 9 rows every 125 s (8 khz). each row contains 621 information bits, 5 stuff control bits, 1 stuff opportunity bit, and 2 overhead communication
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 110 channel bits. fixed stuff bytes are used to fill the remaining bytes. please refer to section 9.27 for a description of the ds3 mapping. 9.32.1 ds3 mapper serializer high speed serial data from the ds3-tran block is deserialized and written into the elastic store. 9.32.2 ds3 mapper elastic store the elastic store block is provided to compensate for frequency differences between the ds3 stream from the ds3-tran block and the sts-1 (stm-0/au3) spe capacity. the ds3 serializer writes data into the elastic store at the ticlk/8 rate while data is read out at the stuffed sts-1 (stm-0/au3) byte rate. if an overflow or underflow condition occurs, an interrupt is optionally asserted and the elastic store read and write address are reset to the startup values (logically 180 degrees apart). the elastic store is 128 bits (16 bytes) to allow for a fixed read/write pointer lag of 7 bytes (3 bytes for toh, 1 byte for poh, 2 bytes for r bits, and 3 overhead bits which is rounded-up to 1 byte). four bytes are also added on either side for positive and negative threshold detection. 9.32.3 ds3 synchronizer the ds3 synchronizer performs the mapping of the ds3 into the sts-1 (stm-0/au3) spe. the ds3 synchronizer monitors the elastic store level to control the stuffing algorithm to avoid overflow (i.e. run faster) and underflow (i.e. run slower) conditions. the fill level of the elastic store is monitored and stuff opportunities in the ds3 mapping are used to center the elastic store. to consume a stuff opportunity, the five c-bits on a row are set to ones and the s bit is used to carry an ds3 information bit. when the s bit is not used to carry information, the c-bits on the row are set to zeros. the ds3 synchronizer uses a fixed bit leaking algorithm which leaks 8 bits of phase buildup in 500 s. the 8 khz sts-1 (stm-0/au3) frame interval is subdivided into 9 rows. each row contains one stuff opportunity. table 8 illustrates the stuffing implementation where s means stuff bit and i means an information bit (ds3 data).
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 111 table 8 - ds3 synchronizer bit stuffing algorithm. row number normal or ds3 ais run faster run slower 1s ss 2s ss 3i i i 4s ss 5s i s 6i is 7s ss 8s i s 9i is under microprocessor control, the incoming ds3 stream can be overwritten with the framed ds3 ais. when asserting ds3 ais, a nominal stuff pattern is used as illustrated above. please refer to the d3md functional description section for a description of the ds3 ais frame. the d3ma outputs the sts-1 (stm-0/au3) with the mapped ds3 onto the line add bus, ladata[7:0]. 9.33 extract scaleable bandwidth interconnect (exsbi) the extract scaleable bandwidth interconnect block demaps up to 84 1.544 mbit/s links, 63 2.048 mbit/s links, three 44.736 mbit/s links, three 34.386 mbit/s links or an arbitary bit rate from the sbi shared bus. the sbi bandwidth is evenly divided into three spes, each of which may carry a different payload type. the 1.544 mbit/s links can be unframed or they can be t1 framed and channelized for insertion into the ds3 multiplex or sonet/sdh mapping. the 2.048 mbit/s links can be unframed or they can be e1 framed and channelized for insertion into the sonet/sdh mapping or g.747 multiplexer. the 44.736 mbit/s links can also be unframed for mapping into sonet/sdh. the 44.736 mbit/s links and 34.368 mbit/s links can be ds3/e3 unchannelized when the temap-84 is used as a ds3/e3 framer. finally, an arbitrary bandwidth signal may be carried for presentation on the flexible bandwidth port. the sbi bus data formats section provides the details of the mapping formats. all egress links extracted from the sbi bus can be timed from the source or from the temap-84. when timing is from the source, the 1.544 mbit/s, 2.048 mbit/s, 34.368 mbit/s or 44.736 mbit/s internal clocks are slaved to the arrival rate of the
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 112 data. for 34.368 mbit/s or 44.736 mbit/s data streams there is also the option of using timing link rate adjustments provided from the source and carried with the links over the sbi bus. a t1/e1 tributary may be transmitted at a rate different from that of the sbi bus if the tributary is looped timed, locked to the ctclk input or locked to a selected recovered clock. in this case, the frame slip buffer (elst) must be used to adapt the data rate. the 44.736 mbit/s or 34.368 mbit/s clock is synthesized from the 51.84 mhz or 44.928 mhz reference clock, clk52m. using either reference clock frequency, the 44.736 mbit/s or 34.368 mbit/s rate is generated by gapping the reference clock in a fixed way. timing adjustments are performed by adding or deleting four clocks over the 500 s period. when the temap-84 is the sbi egress clock master for a link, clocks are sourced from within the temap-84. the data rate is set by the frequency of the ctclk input, one of the three recovered clocks (recvclk1, recvclk2, or recvclk3) or the tributary receive clock if loop timed. based on buffer fill levels, the exsbi sends link rate adjustment commands to the link source indicating that it should send one additional or one fewer bytes of data during the next 500 s interval. failure of the source to respond to these commands will ultimately result in overflows or underflows which can be configured to generate per link interrupts. channelized t1s extracted from the sbi bus optionally have the channel associated signaling (cas) bits explicitly defined and carried in parallel with the ds0s. 9.34 insert scaleable bandwidth interconnect (insbi) the insert scaleable bandwidth interconnect block maps up to 84 1.544 mbit/s links, 63 2.048 mbit/s links, three 44.736 mbit/s links, three 34.386 mbit/s links or an arbitary bit rate into the sbi shared bus. the sbi bandwidth is evenly divided into three spes, each of which may carry a different payload type. the 1.544 mbit/s links will be unframed when sourced directly from the ds3 multiplexer or sonet/sdh bit asynchronous mapper, or they can be t1 channelized when sourced by the sonet/sdh byte synchronous mapper. the 2.048 mbit/s links will be unframed when sourced directly from the sonet/sdh bit asynchronous mapper or g.747 demultiplexer, or they can be e1 channelized when sourced by the sonet/sdh byte synchronous mapper. the 44.736 mbit/s links and 34.368 mbit/s links can also be unframed when sourced directly from the ds3/e3 interfaces or from the ds3 mapper. the 44.736 mbit/s links and 34.368 mbit/s links can be unchannelized ds3/e3s when sourced from the ds3 or e3 framers. finally, an arbitrary bandwidth signal that has been received
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 113 flexible bandwidth port may be output. the sbi bus data formats section provides the details of the mapping formats. links inserted into the sbi bus can be synchronous to the sbi bus (by setting synch_trib=1 in the insbi control ram) or timed from the upstream data source via the sonet/sdh mapper, m13, or ds3/e3 framer. when synch_trib is logic 0, the insbi makes link rate adjustments by adding or deleting an extra byte of data over a 500 s interval based on buffer fill levels. timing adjustments are detected by the receiving sbi interface by explicit signals in the sbi bus structure. when synch_trib is logic 1, the tributary is ?locked? in which no timing adjustments are allowed. the frame slip buffer (elst) must be in the datapath in ?locked? mode. the insbi always sends valid link rate information across the sbi drop bus, which contains both clkrate(1:0) and phase(3:0) field information. this gives an external device receiving data from the insbi three methods of creating a recovered link clock: the clkrate field, the phase field, or just the rate of data flow across the sbi drop bus. insbi does not generate the phase field for ds3/e3 tribs. for byte synchronous mapping applications, channelized t1s inserted into the sbi bus optionally have the channel associated signaling (cas) bits explicitly defined and carried in parallel with the ds0s or timeslots. 9.35 flexible bandwidth ports three flexible bandwidth ports are provided to supply arbitary bandwidth signals to the sbi bus. each port is associated with one spe on the sbi bus and may carry up to the capacity of the spe (49.5 mbit/s). in the ingress direction, data is presented as a three wire interface: a clock of up to 51.84 mhz, bit serial data and an enable. no flow control is provided, so the average data rate must be less than 49.5 mbit/s. in the egress direction, a simple handshake controls the data flow. for each cycle that the efbwdreq[n] input is high, a bit may be output on the efbwdat[n] output. the data is supplied from the sbi bus fifo, which will be kept half full through the sajust_req asserts as required. 9.36 jtag test access port the jtag test access port block provides jtag support for boundary scan. the standard jtag extest, sample, bypass, idcode and stctest
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 114 instructions are supported. the temap-84 identification code is 053660cd hexadecimal.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 115 9.37 microprocessor interface the microprocessor interface block provides normal and test mode registers, the interrupt logic, and the logic required to connect to the microprocessor interface. the normal mode registers are required for normal operation, and test mode registers are used to enhance the testability of the temap-84. the register memory map in table 9 shows where the normal mode registers are accessed. the resulting register organization splits into sections: master configuration registers, t1/e1 registers, ds3 m13 multiplexing registers, sonet/sdh mapping registers and sbi registers. on power up reset the temap-84 defaults to 1.544 kbit/s tributaries multiplexed into the three m13 multiplexers using the ds3 m23 multiplex format. for proper operation some register configuration is necessary. system side access defaults to the sbi bus without any tributaries enabled which will leave the sbi drop bus tristated. by default interrupts will not be enabled, automatic alarm generation is disabled, a dual rail ds3 liu interface is expected and an external transmit reference clock is required. table 9 - register memory map address register 0x0000 revision 0x0001 global reset 0x0002 global configuration 0x0003 spe #1 configuration 0x0004 spe #2 configuration 0x0005 spe #3 configuration 0x0006 bus configuration 0x0007 global performance monitor update 0x0008 reference clock select 0x0009 recovered clock#1 select 0x000a recovered clock#2 select 0x000b recovered clock#3 select
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 116 address register 0x000c master h-mvip interface configuration 0x000d master clock monitor #1 0x0010 master interrupt source 0x0011 master interrupt source t1e1 0x0012 master interrupt source sdh #1 0x0013 master interrupt source sdh #2 0x0014 master interrupt source sdh #3 0x0015 master interrupt source sbi 0x0016 master interrupt source ds3/e3 #1 0x0017 master interrupt source ds2 #1 0x0018 master interrupt source mx12 #1 0x0019 master interrupt source ds3/e3 #2 0x001a master interrupt source ds2 #2 0x001b master interrupt source mx12 #2 0x001c master interrupt source ds3/e3 #3 0x001d master interrupt source ds2 #3 0x001e master interrupt source mx12 #3 0x0020 master sbidet0 collision detect lsb 0x0021 master sbidet0 collision detect msb 0x0022 master sbidet1 collision detect lsb 0x0023 master sbidet1 collision detect msb 0x0040 t1/e1 master configuration 0x0048 rjat indirect status 0x0049 rjat indirect channel address register 0x004a rjat indirect channel data register 0x004c tjat indirect status 0x004d tjat indirect channel address register 0x004e tjat indirect channel data register
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 117 address register 0x0068 rpcc-sbi indirect status/time-slot address 0x0069 rpcc-sbi indirect channel address register 0x006a-0x006e rpcc-sbi indirect channel data registers 0x006f rpcc-sbi configuration bits 0x0070 - 0x007a rpcc-sbi interrupt status 0x007b rpcc-sbi prbs error insertion 0x007c rpcc-sbi prbs error insert status 0x00a0 rx-sbi-elst indirect status 0x00a1 rx-sbi-elst indirect channel address register 0x00a2 rx-sbi-elst indirect channel data register 0x00a4 - 0x00ae rx-sbi-elst slip status 0x00af - 0x00b9 rx-sbi-elst slip direction 0x00ba rx-sbi-elst slip interrupt enable 0x0100 tpcc indirect status/time-slot address 0x0101 tpcc indirect channel address register 0x0102-0x0106 tpcc indirect channel data registers 0x0107 tpcc configuration 0x0108 - 0x0112 tpcc interrupt status 0x0113 tpcc prbs error insertion 0x0114 tpcc prbs error insert status 0x0170 t1/e1 framer indirect status 0x0171 t1/e1 framer indirect channel address register 0x0172 - 0x0186 t1/e1 framer indirect channel data registers 0x0187 t1/e1 framer configuration and status 0x0188 - 0x0192 t1/e1 framer interrupt status 0x01c0 sbi master reset / bus signal monitor 0x01c1 sbi master configuration 0x01c2 sbi bus master configuration
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 118 address register 0x01d0 exsbi control 0x01d1 exsbi fifo underrun interrupt status 0x01d2 exsbi fifo overrun interrupt status 0x01d3 exsbi tributary ram indirect access address 0x01d4 exsbi tributary ram indirect access control 0x01d6 exsbi tributary control indirect access data 0x01d7 sbi parity error interrupt status 0x01de exsbi depth check interrupt status 0x01df extract external resynch interrupt status 0x01e0 insbi control 0x01e1 insbi fifo underrun interrupt status 0x01e2 insbi fifo overrun interrupt status 0x01e3 insbi tributary indirect access address 0x01e4 insbi tributary indirect access control 0x01e6 insbi tributary control indirect access data 0x01f1 insbi depth check interrupt status 0x01f2 insert external resynch interrupt status 0x0200 ? 0x2d5 ds3/e3 framer and m13 multiplex #1 0x0200 ds3 and e3 master reset 0x0201 ds3 and e3 master data source 0x0202 ds3 and e3 master unchannelized interface options 0x0203 ds3/e3 master transmit line options 0x0204 ds3/e3 master receive line options 0x0205 ds3/e3 master alarm enable 0x0206 ds2 master alarm enable / ds3 network requirement bit 0x0207 e3 data link control 0x0208 ds3 tran configuration
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 119 address register 0x0209 ds3 tran diagnostic 0x020c ds3 frmr configuration 0x020d ds3 frmr interrupt enable (ace=0) 0x020d ds3 frmr additional configuration (ace=1) 0x020e ds3 frmr interrupt status 0x020f ds3 frmr status 0x0210 ds3/e3 pmon performance meters 0x0211 ds3/e3 pmon interrupt enable/status 0x0214 ds3/e3 pmon line code violation event count lsb 0x0215 ds3/e3 pmon line code violation event count msb 0x0216 ds3/e3 pmon framing bit error event count lsb 0x0217 ds3/e3 pmon framing bit error event count msb 0x0218 ds3 pmon excessive zeros lsb 0x0219 ds3 pmon excessive zeros msb 0x021a ds3/e3 pmon parity error event count lsb 0x021b ds3/e3 pmon parity error event count msb 0x021c ds3 pmon path parity error event count lsb 0x021d ds3 pmon path parity error event count msb 0x021e ds3/e3 pmon febe event count lsb 0x021f ds3/e3 pmon febe event count msb 0x0220 ds3/e3 tdpr configuration 0x0221 ds3/e3 tdpr upper transmit threshold 0x0222 ds3/e3 tdpr lower interrupt threshold 0x0223 ds3/e3 tdpr interrupt enable 0x0224 ds3/e3 tdpr interrupt status/udr clear 0x0225 ds3/e3 tdpr transmit data 0x0228 ds3/e3 rdlc configuration
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 120 address register 0x0229 ds3/e3 rdlc interrupt control 0x022a ds3/e3 rdlc status 0x022b ds3/e3 rdlc data 0x022c ds3/e3 rdlc primary address match 0x022d ds3/e3 rdlc secondary address match 0x0230 prgd control 0x0231 prgd interrupt enable/status 0x0232 prgd length 0x0233 prgd tap 0x0234 prgd error insertion 0x0238 prgd pattern insertion #1 0x0239 prgd pattern insertion #2 0x023a prgd pattern insertion #3 0x023b prgd pattern insertion #4 0x023c prgd pattern detector #1 0x023d prgd pattern detector #2 0x023e prgd pattern detector #3 0x023f prgd pattern detector #4 0x0240 mx23 configuration 0x0241 mx23 demux ais insert 0x0242 mx23 mux ais insert 0x0243 mx23 loopback activate 0x0244 mx23 loopback request insert 0x0245 mx23 loopback request detect 0x0246 mx23 loopback request interrupt 0x0248 feac xboc control 0x0249 feac xboc code 0x024a feac rboc configuration/interrupt enable
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 121 address register 0x024b feac rboc interrupt status 0x0250 ds2 frmr #1 configuration 0x0251 ds2 frmr #1 interrupt enable 0x0252 ds2 frmr #1 interrupt status 0x0253 ds2 frmr #1 status 0x0254 ds2 frmr #1 monitor interrupt enable/status 0x0255 ds2 frmr #1 ferr count 0x0256 ds2 frmr #1 perr count (lsb) 0x0257 ds2 frmr #1 perr count (msb) 0x0258 mx12 #1configuration and control 0x0259 mx12 #1 loopback code select 0x025a mx12 #1 mux/demux ais insert 0x025b mx12 #1 loopback activate 0x025c mx12 #1 loopback interrupt 0x0260 ds2 frmr #2 registers 0x0268 mx12 #2 registers 0x0270 ds2 frmr #3 registers 0x0278 mx12 #3 registers 0x0280 ds2 frmr #4 registers 0x0288 mx12 #4 registers 0x0290 ds2 frmr #5 registers 0x0298 mx12 #5 registers 0x02a0 ds2 frmr #6 registers 0x02a8 mx12 #6 registers 0x02b0 ds2 frmr #7 registers 0x02b8 mx12 #7 registers 0x02c0 e3 frmr framing options 0x02c1 e3 frmr maintenance options
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 122 address register 0x02c2 e3 frmr framing interrupt enable 0x02c3 e3 frmr framing interrupt indication and status 0x02c4 e3 frmr maintenance event interrupt enable 0x02c5 e3 frmr maintenance event interrupt indication 0x02c6 e3 frmr maintenance event status 0x02c8 e3 tran framing options 0x02c9 e3 tran status and diagnostic options 0x02ca e3 tran bip-8 error mask 0x02cb e3 tran maintenance and adaptation options 0x02d0 ttb control 0x02d1 ttb trail trace identifier status 0x02d2 ttb indirect address 0x02d3 ttb indirect data 0x02d4 ttb expected payload type label 0x02d5 ttb payload type label control/status 0x0300 ? 0x03d5 ds3/e3 framer and m13 multiplex #2 0x0400 ? 0x04d5 ds3/e3 framer and m13 multiplex #3 0x0700 sonet/sdh master reset 0x0701 sonet/sdh master ingress configuration 0x0702 sonet/sdh master egress configuration 0x0703 sonet/sdh master ingress vtpp configuration 0x0704 sonet/sdh master egress vtpp configuration 0x0705 sonet/sdh master rtop configuration 0x0706 sonet/sdh master tributary alarm ais control 0x0707 sonet/sdh master tributary remote defect indication control 0x0708 sonet/sdh master tributary auxiliary remote defect indication control
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 123 address register 0x0709 sonet/sdh master ds3/e3 clock generation control 0x070a sonet/sdh master loopback control 0x070b sonet/sdh telecom bus signal monitor, accumulation trigger 0x070c sonet/sdh transmit pointer configuration #1 (msb) 0x070d sonet/sdh transmit pointer configuration #2 (lsb) 0x740 - 0x077f ingress vtpp #1 0x0740, 0x0742, 0x0744, 0x0746, 0x0748, 0x074a, 0x074c vtpp ingress, tu #1 in tug2 #1 to tug2 #7, configuration and status 0x0741, 0x0743, 0x0745, 0x0747, 0x0749, 0x074b, 0x074d vtpp ingress, tu #1 in tug2 #1 to tug2 #7, alarm status 0x074e vtpp ingress, tu #1 in tug2 #1 to tug2 #7, lop interrupt 0x074f vtpp ingress, tu #1 in tug2 #1 to tug2 #7, ais interrupt 0x0750, 0x0752, 0x0754, 0x0756, 0x0758, 0x075a, 0x075c vtpp ingress, tu #2 in tug2 #1 to tug2 #7, configuration and status 0x0751, 0x0753, 0x0755, 0x0757, 0x0759, 0x075b, 0x075d vtpp ingress, tu #2 in tug2 #1 to tug2 #7, alarm status 0x075e vtpp ingress, tu #2 in tug2 #1 to tug2 #7, lop interrupt 0x075f vtpp ingress, tu #2 in tug2 #1 to tug2 #7 ais interrupt
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 124 address register 0x0760, 0x0762, 0x0764, 0x0766, 0x0768, 0x076a, 0x076c vtpp ingress, tu #3 in tug2 #1 to tug2 #7, configuration and status 0x0761, 0x0763, 0x0765, 0x0767, 0x0769, 0x076b, 0x076d vtpp ingress, tu #3 in tug2 #1 to tug2 #7, alarm status 0x076e vtpp ingress, tu #3 in tug2 #1 to tug2 #7, lop interrupt 0x076f vtpp ingress, tu #3 in tug2 #1 to tug2 #7, ais interrupt 0x0770, 0x0772, 0x0774, 0x0776, 0x0778, 0x077a, 0x077c vtpp ingress, tu #4 in tug2 #1 to tug2 #7, configuration and status 0x0771, 0x0773, 0x0775, 0x0777, 0x0779, 0x077b, 0x077d vtpp ingress, tu #4 in tug2 #1 to tug2 #7, alarm status 0x077e vtpp ingress, tu #4 in tug2 #1 to tug2 #7, lop interrupt 0x077f vtpp ingress, tu #4 in tug2 #1 to tug2 #7, ais interrupt 0x780 - 0x07bf ingress vtpp #2 0x7c0 - 0x07ff ingress vtpp #3 0x0800 - 0x85e rtdm tributary control 0x0860 reserved 0x0862 rtdm time switch page control 0x0863 rtdm indirect time switch tributary ram status and control 0x0864 rtdm indirect time switch internal link address 0x0865 rtdm indirect ingress tributary data 0x0900 ? 0x93f egress vtpp #1
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 125 address register 0x0900, 0x0902, 0x0904, 0x0906, 0x0908, 0x090a, 0x090c vtpp egress, tu #1 in tug2 #1 to tug2 #7, configuration and status 0x0901, 0x0903, 0x0905, 0x0907, 0x0909, 0x090b, 0x090d vtpp egress, tu #1 in tug2 #1 to tug2 #7, alarm status 0x090e vtpp egress, tu #1 in tug2 #1 to tug2 #7, lop interrupt 0x090f vtpp egress, tu #1 in tug2 #1 to tug2 #7, ais interrupt 0x0910, 0x0912, 0x0914, 0x0916, 0x0918, 0x091a, 0x091c vtpp egress, tu #2 in tug2 #1 to tug2 #7, configuration and status 0x0911, 0x0913, 0x0915, 0x0917, 0x0919, 0x091b, 0x091d vtpp egress, tu #2 in tug2 #1 to tug2 #7, alarm status 0x091e vtpp egress, tu #2 in tug2 #1 to tug2 #7, lop interrupt 0x091f vtpp egress, tu #2 in tug2 #1 to tug2 #7 ais interrupt 0x0920, 0x0922, 0x0924, 0x0926, 0x0928, 0x092a, 0x092c vtpp egress, tu #3 in tug2 #1 to tug2 #7, configuration and status 0x0921, 0x0923, 0x0925, 0x0927, 0x0929, 0x092b, 0x092d vtpp egress, tu #3 in tug2 #1 to tug2 #7, alarm status 0x092e vtpp egress, tu #3 in tug2 #1 to tug2 #7, lop interrupt 0x092f vtpp egress, tu #3 in tug2 #1 to tug2 #7, ais interrupt
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 126 address register 0x0930, 0x0932, 0x0934, 0x0936, 0x0938, 0x093a, 0x093c vtpp egress, tu #4 in tug2 #1 to tug2 #7, configuration and status 0x0931, 0x0933, 0x0935, 0x0937, 0x0939, 0x093b, 0x093d vtpp egress, tu #4 in tug2 #1 to tug2 #7, alarm status 0x093e vtpp egress, tu #4 in tug2 #1 to tug2 #7, lop interrupt 0x093f vtpp egress, tu #4 in tug2 #1 to tug2 #7, ais interrupt 0x0940 ? 0x97f egress vtpp #2 0x0980 ? 0x9bf egress vtpp #3 0x09c0 byte synchronous mapping control register 0x09c3 byte synchronous mapping tributary indirect access address register 0x09c4 byte synchronous mapping tributary indirect access control register 0x09c5 byte synchronous mapping tributary mapping indirect access data register 0x09c6 byte synchronous mapping tributary control indirect access data register 0x09e0 byte synchronous demapping control register 0x09e3 byte synchronous demapping tributary ram indirect access address register 0x09e4 byte synchronous demapping tributary ram indirect access control register 0x09e5 byte synchronous demapping tributary mapping ram indirect access data register 0x09e6 byte synchronous demapping tributary control ram indirect access data register 0x0x9ef byte synchronous demapping fifo control register
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 127 address register 0x0a00 ? 0x0afd receive tributary overhead processor (rtop) #1 0x0a00, 0x0a08, 0x0a10, 0x0a18, 0x0a20, 0x0a28, 0x0a30 rtop, tu #1 in tug2 #1 to tug2 #7, configuration 0x0a01, 0x0a09, 0x0a11, 0x0a19, 0x0a21, 0x0a29, 0x0a31 rtop, tu #1 in tug2 #1 to tug2 #7, configuration and alarm status 0x0a02, 0x0a0a, 0x0a12, 0x0a1a, 0x0a22, 0x0a2a, 0x0a32 rtop, tu #1 in tug2 #1 to tug2 #7, expected path signal label 0x0a03, 0x0a0b, 0x0a13, 0x0a1b, 0x0a23, 0x0a2b, 0x0a33 rtop, tu #1 in tug2 #1 to tug2 #7, accepted path signal label 0x0a04, 0x0a0c, 0x0a14, 0x0a1c, 0x0a24, 0x0a2c, 0x0a34 rtop, tu #1 in tug2 #1 to tug2 #7, bip-2 error count lsb 0x0a05, 0x0a0d, 0x0a15, 0x0a1d, 0x0a25, 0x0a2d, 0x0a35 rtop, tu #1 in tug2 #1 to tug2 #7, bip-2 error count msb 0x0a06, 0x0a0e, 0x0a16, 0x0a1e, 0x0a26, 0x0a2e, 0x0a36 rtop, tu #1 in tug2 #2 to tug2 #7, febe error count lsb 0x0a07, 0x0a0f, 0x0a17, 0x0a1f, 0x0a27, 0x0a2f, 0x0a37 rtop, tu #1 in tug2 #2 to tug2 #7, febe error count msb 0x0a38 rtop, tu #1 in tug2 #1 to tug2 #7, copsl interrupt
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 128 address register 0x0a39 rtop, tu #1 in tug2 #1 to tug2 #7, pslm interrupt 0x0a3a rtop, tu #1 in tug2 #1 to tug2 #7, pslu interrupt 0x0a3b rtop, tu #1 in tug2 #1 to tug2 #7, rdi interrupt 0x0a3c rtop, tu #1 in tug2 #1 to tug2 #7 rfi interrupt 0x0a3d rtop, tu #1 in tug2 #1 to tug2 #7, inband error reporting configuration 0x0a40, 0x0a48, 0x0a50, 0x0a58, 0x0a60, 0x0a68, 0x0a70 rtop, tu #2 in tug2 #1 to tug2 #7, configuration 0x0a41, 0x0a49, 0x0a51, 0x0a59, 0x0a61, 0x0a69, 0x0a71 rtop, tu #2 in tug2 #1 to tug2 #7, configuration and alarm status 0x0a42, 0x0a4a, 0x0a52, 0x0a5a, 0x0a62, 0x0a6a, 0x0a72 rtop, tu #2 in tug2 #1 to tug2 #7, expected path signal label 0x0a43, 0x0a4b, 0x0a53, 0x0a5b, 0x0a63, 0x0a6b, 0x0a73 rtop, tu #2 in tug2 #1 to tug2 #7, accepted path signal label 0x0a44, 0x0a4c, 0x0a54, 0x0a5c, 0x0a64, 0x0a6c, 0x0a74 rtop, tu #2 in tug2 #1 to tug2 #7, bip-2 error count lsb 0x0a45, 0x0a4d, 0x0a55, 0x0a5d, 0x0a65, 0x0a6d, 0x0a75 rtop, tu #2 in tug2 #1 to tug2 #7, bip-2 error count msb 0x0a46, 0x0a4e, 0x0a56, 0x0a5e, 0x0a66, 0x0a6e, 0x0a76 rtop, tu #2 in tug2 #1 to tug2 #7, febe error count lsb
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 129 address register 0x0a47, 0x0a4f, 0x0a57, 0x0a5f, 0x0a67, 0x0a6f, 0x0a77 rtop, tu #2 in tug2 #1 to tug2 #7, febe error count msb 0x0a78 rtop, tu #2 in tug2 #1 to tug2 #7, copsl interrupt 0x0a79 rtop, tu #2 in tug2 #1 to tug2 #7, pslm interrupt 0x0a7a rtop, tu #2 in tug2 #1 to tug2 #7, pslu interrupt 0x0a7b rtop, tu #2 in tug2 #1 to tug2 #7, rdi interrupt 0x0a7c rtop, tu #2 in tug2 #1 to tug2 #7, rfi interrupt 0x0a7d rtop, tu #2 in tug2 #1 to tug2 #7, inband error reporting configuration 0x0a80, 0x0a88, 0x0a90, 0x0a98, 0x0aa0, 0x0aa8, 0x0ab0 rtop, tu #3 in tug2 #1 to tug2 #7, configuration 0x0a81, 0x0a89, 0x0a91, 0x0a99, 0x0aa1, 0x0aa9, 0x0ab1 rtop, tu #3 in tug2 #1 to tug2 #7, configuration and alarm status 0x0a82, 0x0a8a, 0x0a92, 0x0a9a, 0x0aa2, 0x0aaa, 0x0ab2 rtop, tu #3 in tug2 #1 to tug2 #7, expected path signal label 0x0a83, 0x0a8b, 0x0a93, 0x0a9b, 0x0aa3, 0x0aab, 0x0ab3 rtop, tu #3 in tug2 #1 to tug2 #7, accepted path signal label 0x0a84, 0x0a8c, 0x0a94, 0x0a9c, 0x0aa4, 0x0aac, 0x0ab4 rtop, tu #3 in tug2 #1 to tug2 #7, bip-2 error count lsb
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 130 address register 0x0a85, 0x0a8d, 0x0a95, 0x0a9d, 0x0aa5, 0x0aad, 0x0ab5 rtop, tu #3 in tug2 #1 to tug2 #7, bip-2 error count msb 0x0a86, 0x0a8e, 0x0a96, 0x0a9e, 0x0aa6, 0x0aae, 0x0ab6 tu #3 in tug2 #1 to tug2 #7, febe error count lsb 0x0a87, 0x0a8f, 0x0a97, 0x0a9f, 0x0aa7, 0x0aaf, 0x0ab7 rtop, tu #3 in tug2 #1 to tug2 #7, febe error count msb 0x0ab8 rtop, tu #3 in tug2 #1 to tug2 #7, copsl interrupt 0x0ab9 rtop, tu #3 in tug2 #1 to tug2 #7, pslm interrupt 0x0aba rtop, tu #3 in tug2 #1 to tug2 #7, pslu interrupt 0x0abb rtop, tu #3 in tug2 #1 to tug2 #7, rdi interrupt 0x0abc rtop, tu #3 in tug2 #1 to tug2 #7, rfi interrupt 0x0abd rtop, tu #3 in tug2 #1 to tug2 #7, inband error reporting configuration 0x0ac0, 0x0ac8, 0x0ad0, 0x0ad8, 0x0ae0, 0x0ae8, 0x0af0 rtop, tu #4 in tug2 #1 to tug2 #7, configuration 0x0ac1, 0x0ac9, 0x0ad1, 0x0ad9, 0x0ae1, 0x0ae9, 0x0af1 rtop, tu #4 in tug2 #1 to tug2 #7, configuration and alarm status 0x0ac2, 0x0aca, 0x0ad2, 0x0ada, 0x0ae2, 0x0aea, 0x0af2 rtop, tu #4 in tug2 #1 to tug2 #7, expected path signal label
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 131 address register 0x0ac3, 0x0acb, 0x0ad3, 0x0adb, 0x0ae3, 0x0aeb, 0x0af3 rtop, tu #4 in tug2 #1 to tug2 #7, path signal label 0x0ac4, 0x0acc, 0x0ad4, 0x0adc, 0x0ae4, 0x0aec, 0x0af4 rtop, tu #4 in tug2 #1 to tug2 #7, bip-2 error count lsb 0x0ac5, 0x0acd, 0x0ad5, 0x0add, 0x0ae5, 0x0aed, 0x0af5 rtop, tu #4 in tug2 #1 to tug2 #7, bip-2 error count msb 0x0ac6, 0x0ace, 0x0ad6, 0x0ade, 0x0ae6, 0x0aee, 0x0af6 rtop, tu #4 in tug2 #1 to tug2 #7, febe error count lsb 0x0ac7, 0x0acf, 0x0ad7, 0x0adf, 0x0ae7, 0x0aef, 0x0af7 rtop, tu #4 in tug2 #1 to tug2 #7, febe error count msb 0x0af8 rtop, tu #4 in tug2 #1 to tug2 #7, copsl interrupt 0x0af9 rtop, tu #4 in tug2 #1 to tug2 #7, pslm interrupt 0x0afa rtop, tu #4 in tug2 #1 to tug2 #7, pslu interrupt 0x0afb rtop, tu #4 in tug2 #1 to tug2 #7, rdi interrupt 0x0afc rtop, tu #4 in tug2 #1 to tug2 #7, rfi interrupt 0x0afd rtop, tu #4 in tug2 #1 to tug2 #7, inband error reporting configuration 0x0b00 ? 0x0bfd receive tributary overhead processor (rtop) #2 0x0c00 ? 0x0cfd receive tributary overhead processor (rtop) #3
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 132 address register 0x0d00 - 0x0d06 trap tu #1 in tug2 #1 to tug2 #7 of tug3 #1, control 0x0d07 trap tu #1 in tug2 #1 to tug2 #7 of tug3 #1, egress ais control 0x0d08 - 0x0d0e trap tu #2 in tug2 #1 to tug2 #7 of tug3 #1, control 0x0d0f trap tu #2 in tug2 #1 to tug2 #7 of tug3 #1, egress ais control 0x0d10 - 0x0d16 trap tu #3 in tug2 #1 to tug2 #7 of tug3 #1 control 0x0d17 trap tu #3 in tug2 #1 to tug2 #7 of tug3 #1, egress ais control 0x0d18 - 0x0d1e trap tu #4 in tug2 #1 to tug2 #7 of tug3 #1, control 0x0d1f trap tu #4 in tug2 #1 to tug2 #7 of tug3 #1, egress ais control 0x0d20 - 0x0d26 trap tu #1 in tug2 #1 to tug2 #7 of tug3 #2, control 0x0d27 trap tu #1 in tug2 #1 to tug2 #7 of tug3 #2, egress ais control 0x0d28 - 0x0d2e trap tu #2 in tug2 #1 to tug2 #7 of tug3 #2, control 0x0d2f trap tu #2 in tug2 #1 to tug2 #7 of tug3 #2, egress ais control 0x0d30 - 0x0d36 trap tu #3 in tug2 #1 to tug2 #7 of tug3 #2, control 0x0d37 trap tu #3 in tug2 #1 to tug2 #7 of tug3 #2, egress ais control 0x0d38 - 0x0d3e trap tu #4 in tug2 #1 to tug2 #7 of tug3 #2, control 0x0d3f trap tu #4 in tug2 #1 to tug2 #7 of tug3 #2, egress ais control 0x0d40 - 0x0d46 trap tu #1 in tug2 #1 to tug2 #7 of tug3 #3, control
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 133 address register 0x0d47 trap tu #1 in tug2 #1 to tug2 #7 of tug3 #3, egress ais control 0x0d48 - 0x0d4e trap tu #2 in tug2 #1 to tug2 #7 of tug3 #3, control 0x0d4f trap tu #2 in tug2 #1 to tug2 #7 of tug3 #3, egress ais control 0x0d50 - 0x0d56 trap tu #3 in tug2 #1 to tug2 #7 of tug3 #3, control 0x0d57 trap tu #3 in tug2 #1 to tug2 #7 of tug3 #3, egress ais control 0x0d58 - 0x0d5e trap tu #4 in tug2 #1 to tug2 #7 of tug3 #3, control 0x0d5f trap tu #4 in tug2 #1 to tug2 #7 of tug3 #3, egress ais control 0x0d60 trap indirect remote alarm page address 0x0d61 trap indirect remote alarm tributary address 0x0d62 trap indirect datapath tributary data 0x0d63 trap rdi control 0x0d68 trap remote parallel alarm port tug2 #1 of tug3 #1 configuration 0x0d69- 0x0d6e trap remote parallel alarm port tug2 #2 to tug2 #7 of tug3 #1 configuration 0x0d70 - 0x0d76 trap remote parallel alarm port tug2 #1 to tug2 #7 of tug3 #2 configuration 0x0d78 - 0x0d7e trap remote parallel alarm port tug2 #1 to tug2 #7 of tug3 #3 configuration 0x0d80 ttop tu #1 in tug2 #1 of tug3 #1, control 0x0d81 - 0x0d86 ttop tu #1 in tug2 #2 to tug2 #7 of tug3 #1, control 0x0d87 ttop tu #1 in tug2 #1 to tug2 #7 of tug3 #1 bip diagnostic control 0x0d88 - 0x0d8e ttop tu #2 in tug2 #1 to tug2 #7 of tug3 #1, control
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 134 address register 0x0d8f ttop tu #2 in tug2 #1 to tug2 #7 of tug3 #1 bip diagnostic control 0x0d90 - 0x0d96 ttop tu #3 in tug2 #1 to tug2 #7 of tug3 #1, control 0x0d97 ttop tu #3 in tug2 #1 to tug2 #7 of tug3 #1, bip diagnostic control 0x0d98 - 0x0d9e ttop tu #4 in tug2 #1 to tug2 #7 of tug3 #1, control 0x0d9f ttop tu #4 in tug2 #1 to tug2 #7 of tug3 #1, bip diagnostic control 0x0da0 - 0x0da6 ttop tu #1 in tug2 #1 to tug2 #7 of tug3 #2, control 0x0da7 ttop tu #1 in tug2 #1 to tug2 #7 of tug3 #2, bip diagnostic control 0x0da8 - 0x0dae ttop tu #2 in tug2 #1 to tug2 #7 of tug3 #2, control 0x0daf ttop tu #2 in tug2 #1 to tug2 #7 of tug3 #2, bip diagnostic control 0x0db0 - 0x0db6 tu #3 in tug2 #1 to tug2 #7 of tug3 #2, control 0x0db7 ttop tu #3 in tug2 #1 to tug2 #7 of tug3 #2, bip diagnostic control 0x0db8 - 0x0dbe ttop tu #4 in tug2 #1 to tug2 #7 of tug3 #2, control 0x0dbf ttop tu #4 in tug2 #1 to tug2 #7 of tug3 #2, bip diagnostic control 0x0dc0 - 0x0dc6 ttop tu #1 in tug2 #1 to tug2 #7 of tug3 #3, control 0x0dc7 ttop tu #1 in tug2 #1 to tug2 #7 of tug3 #3, bip diagnostic control 0x0dc8 - 0x0dce ttop tu #2 in tug2 #1 to tug2 #7 of tug3 #3, control 0x0dcf ttop tu #2 in tug2 #1 to tug2 #7 of tug3 #3, bip diagnostic control
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 135 address register 0x0dd0 - 0x0dd6 ttop tu #3 in tug2 #1 to tug2 #7 of tug3 #3, control 0x0dd7 ttop tu #3 in tug2 #1 to tug2 #7 of tug3 #3, bip diagnostic control 0x0dd8 - 0x0dde ttop tu #4 in tug2 #1 to tug2 #7 of tug3 #3, control 0x0ddf ttop tu #4 in tug2 #1 to tug2 #7 of tug3 #3, bip diagnostic control 0x0de0 ttop tug3 #1 control 0x0de1 ttop tug3 #2 control 0x0de2 ttop tug3 #3 control 0x0de4 ttop trail trace identifier page select 0x0de5 ttop indirect trail trace identifier tributary select 0x0de6 ttop indirect trail trace identifier buffer address 0x0de7 ttop indirect trail trace identifier buffer data 0x0e00 - 0x0e5e ttmp tributary control 0x0e61 ttmp time switch page control 0x0e62 ttmp indirect time switch ram control and status 0x0e63 ttmp indirect egress tributary address 0x0e64 ttmp indirect time switch internal link data 0x0e65 ttmp telecom interface configuration 0x0e80 ? 0x0e82 d3md #1 0x0e80 d3md control 0x0e81 d3md interrupt status 0x0e82 d3md interrupt enable 0x0e84 ? 0x0e86 d3md #2 0x0e88 ? 0x0e8a d3md #3 0x0e8c ? 0x0e8e d3ma #1 0x0e8c d3ma control
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 136 address register 0x0e8d d3ma interrupt status 0x0e8e d3ma interrupt enable 0x0e90 ? 0x0e92 d3ma #2 0x0e94 ? 0x0e96 d3ma #3 0x0f00 ? 0x0f2b rttb #1 0x0f00 rttb tu3 or tu #1 in tug2 #1, configuration and status 0x0f01 to 0x0f06 rttb tu #1 in tug2 #2 to tug2 #7, configuration and status 0x0f08 to 0x0f0e rttb tu #2 in tug2 #1 to tug2 #7, configuration and status 0x0f10h to 0x0f16 rttb tu #3 in tug2 #1 to tug2 #7, configuration and status 0x0f18 to 0x0f1e rttb tu #4 in tug2 #1 to tug2 #7, configuration and status 0x0f20 + 0x0f20*n rttb tu3 or tu #1 in tug2 #1 to tug2 #7, tim interrupt 0x0f21 rttb tu #2 in tug2 #1 to tug2 #7, tim interrupt 0x0f22 rttb tu #3 in tug2 #1 to tug2 #7, tim interrupt 0x0f23 rttb tu #4 in tug2 #1 to tug2 #7, tim interrupt 0x0f24 rttb tu3 or tu #1 in tug2 #1 to tug2 #7, tiu interrupt 0x0f25 rttb tu #2 in tug2 #1 to tug2 #7, tiu interrupt 0x0f26 rttb tu #3 in tug2 #1 to tug2 #7, tiu interrupt 0x0f27 rttb tu #4 in tug2 #1 to tug2 #7, tiu interrupt 0x0f28 rttb tiu threshold 0x0f29 rttb indirect tributary select 0x0f2a rttb indirect address select 0x0f2b rttb indirect data select 0x0f40 ? 0x0f6b rttb #2
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 137 address register 0x0f80 ? 0x0fab rttb #3 0x1000 master test for all register accesses, csb must be low.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 138 10 normal mode register description normal mode registers are used to configure and monitor the operation of the temap-84. normal mode registers (as opposed to test mode registers) are selected when trs (a[12]) is low. the register descriptions are contained in a separate temap-84 register description document. notes on normal mode register bits: 1) writing values into unused register bits typically has no effect. however, to ensure software compatibility with future, feature-enhanced versions of the product, unused register bit must be written with logic 0. reading back unused bits can produce either a logic 1 or a logic 0; hence unused register bits should be masked off by software when read. 2) all configuration bits that can be written into can also be read back. this allows the processor controlling the temap-84 to determine the programming state of the block. 3) writeable normal mode register bits are cleared to logic 0 upon reset unless otherwise noted. 4) writing into read-only normal mode register bit locations does not affect temap-84 operation unless otherwise noted.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 139 11 test features description the temap-84 contains test features for both production testing and board testing. simultaneously asserting the csb, rdb and wrb inputs causes all output pins and the data bus to be held in a high-impedance state. this test feature may be used for board testing. test mode registers are used to apply test vectors during production testing of the temap-84. test mode registers (as opposed to normal mode registers) are selected when trs (a[12]) is high. notes on register bits: 1) writing values into unused register bits has no effect. reading back unused bits can produce either a logic one or a logic zero; hence unused bits should be masked off by software when read. 2) writeable register bits are not initialized upon reset unless otherwise noted.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 140 register 0x1000: master test register bit type function default bit 7 r/w reserved 0 bit 6 unused x bit 5 unused x bit 4 r/w pmctst 0 bit 3 w dbctrl x bit 2 r/w reserved 0 bit 1 w hizdata x bit 0 r/w hizio 0 this register is used to select temap-84 test features. all bits, except for pmctst, are reset to zero by a hardware reset of the temap-84; a software reset of the temap-84 does not affect the state of the bits in this register. pmctst: the pmctst bit is used to configure the temap-84 for pmc's manufacturing tests. when pmctst is set to logic 1, the temap-84 microprocessor port becomes the test access port used to run the pmc "canned" manufacturing test vectors. the pmctst bit can only be cleared by setting csb to logic 1. dbctrl: the dbctrl bit is used to pass control of the data bus drivers to the csb pin while pmctst is a logic 1. when the dbctrl bit is set to logic 1, the csb pin controls the output enable for the data bus. while the dbctrl bit is set, holding the csb pin high causes the temap-84 to drive the data bus and holding the csb pin low tri-states the data bus. the dbctrl bit overrides the hizdata bit. the dbctrl bit is used to measure the drive capability of the data bus driver pads. when pmctst is logic 0, the dbctrl bit is ignored. reserved: these bits must be logic 0 for correct operation.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 141 hizio: the hizio bit controls the tri-state modes of the output pins of the temap- 84. while the hizio bit is a logic 1, all output pins of the temap-84, except the data bus, are held in a high-impedance state. the microprocessor interface is still active. hizdata: the hizdata bit controls the tri-state modes of the temap-84. while the hizio bit is a logic 1, all output pins of the temap-84, except the data bus, are held in a high-impedance state. while the hizdata bit is a logic 1, the data bus is held in a high-impedance state which inhibits microprocessor read cycles.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 142 11.1 jtag test port the temap-84 jtag test access port (tap) allows access to the tap controller and the 4 tap registers: instruction, bypass, device identification and boundary scan. using the tap, device input logic levels can be read, device outputs can be forced, the device can be identified and the device scan path can be bypassed. for more details on the jtag port, please refer to the operations section. table 10 - instruction register length - 3 bits instructions selected register instruction codes, ir[2:0] extest boundary scan 000 idcode identification 001 sample boundary scan 010 bypass bypass 011 bypass bypass 100 stctest boundary scan 101 bypass bypass 110 bypass bypass 111 table 11 - identification register length 32 bits version number 0x0 part number 0x5366 manufacturer's identification code 0x0cd device identification 0x053660cd
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 143 the boundary scan register is made up of 302 boundary scan cells, divided into input observation (in_cell), output (out_cell) and bidirectional (io_cell) cells. these cells are detailed in the following pages. the first 32 cells form the id code register and carry the code 053660cdh. the boundary scan chain order is presented in table 12. table 12 - boundary scan register pin/ enable bit # cell type id bit pin/ enable bit # cell type id bit sdc1fp 0 io_cell - oeb_d_3 151 out_cell - oeb_sdc1fp 1 out_cell - d_4 152 io_cell - sbiact 2 out_cell - oeb_d_4 153 out_cell - oeb_sbiact 3 out_cell - d_5 154 io_cell - sajust_req 4 out_cell - oeb_d_5 155 out_cell - oeb_sajust_req 5 out_cell - d_6 156 io_cell - sddata_0 6 out_cell - oeb_d_6 157 out_cell - oeb_sddata_0 7 out_cell - d_7 158 io_cell - sddata_1 8 out_cell - oeb_d_7 159 out_cell - oeb_sddata_1 9 out_cell - ale 160 in_cell - sddata_2 10 out_cell - rstb 161 in_cell - oeb_sddata_2 11 out_cell - a_0 162 in_cell - sddata_3 12 out_cell - a_1 163 in_cell - oeb_sddata_3 13 out_cell - a_2 164 in_cell - sddata_4 14 out_cell - a_3 165 in_cell - oeb_sddata_4 15 out_cell - a_4 166 in_cell - sddata_5 16 out_cell - a_5 167 in_cell - oeb_sddata_5 17 out_cell - a_6 168 in_cell - sddata_6 18 out_cell - a_7 169 in_cell - oeb_sddata_6 19 out_cell - a_8 170 in_cell - sddata_7 20 out_cell - a_9 171 in_cell - oeb_sddata_7 21 out_cell - a_10 172 in_cell - sddp 22 out_cell - a_11 173 in_cell - oeb_sddp 23 out_cell - a_12 174 in_cell - sdpl 24 out_cell - wrb 175 in_cell - oeb_sdpl 25 out_cell - rdb 176 in_cell -
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 144 pin/ enable bit # cell type id bit pin/ enable bit # cell type id bit sdv5 26 out_cell - csb 177 in_cell - oeb_sdv5 27 out_cell - lav5 178 out_cell - unconnected 28 out_cell - oeb_lav5 179 out_cell - unconnected 29 out_cell - lapl 180 out_cell - unconnected 30 out_cell - oeb_lapl 181 out_cell - unconnected 31 out_cell - ladp 182 out_cell - unconnected 32 out_cell - oeb_ladp 183 out_cell - unconnected 33 out_cell - ladata_0 184 out_cell - unconnected 34 out_cell - oeb_ladata_0 185 out_cell - unconnected 35 out_cell - ladata_1 186 out_cell - unconnected 36 out_cell - oeb_ladata_1 187 out_cell - unconnected 37 out_cell - ladata_2 188 out_cell - unconnected 38 out_cell - oeb_ladata_2 189 out_cell - unconnected 39 out_cell - ladata_3 190 out_cell - unconnected 40 out_cell - oeb_ladata_3 191 out_cell - unconnected 41 out_cell - ladata_4 192 out_cell - srefclk 42 in_cell - oeb_ladata_4 193 out_cell - unconnected 43 in_cell - ladata_5 194 out_cell - unconnected 44 in_cell - oeb_ladata_5 195 out_cell - s77 45 in_cell - ladata_6 196 out_cell - sac1fp 46 in_cell - oeb_ladata_6 197 out_cell - sadata_0 47 in_cell - ladata_7 198 out_cell - sadata_1 48 in_cell - oeb_ladata_7 199 out_cell - sadata_2 49 in_cell - laoe/latpl 200 out_cell - sadata_3 50 in_cell - oeb_laoe 201 out_cell - sadata_4 51 in_cell - lac1j1v1 202 out_cell - sadata_5 52 in_cell - oeb_lac1j1v1 203 out_cell - sadata_6 53 in_cell - lac1 204 in_cell - sadata_7 54 in_cell - clk52m 205 in_cell - sadp 55 in_cell - radwest 206 in_cell - sapl 56 in_cell - radwestfp 207 in_cell - sav5 57 in_cell - radwestck 208 in_cell -
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 145 pin/ enable bit # cell type id bit pin/ enable bit # cell type id bit sbidet_0 58 in_cell - radeast 209 in_cell - sbidet_1 59 in_cell - radeastfp 210 in_cell - unconnected 60 in_cell - radeastck 211 in_cell - unconnected 61 out_cell - ldais 212 in_cell - unconnected 62 out_cell - ldtpl 213 in_cell - unconnected 63 in_cell - ldv5 214 in_cell - unconnected 64 in_cell - ldpl 215 in_cell - unconnected 65 in_cell - ldc1j1v1 216 in_cell - unconnected 66 out_cell - lddp 217 in_cell - unconnected 67 out_cell - lddata_0 218 in_cell - unconnected 68 out_cell - lddata_1 219 in_cell - unconnected 69 out_cell - lddata_2 220 in_cell - unconnected 70 out_cell - lddata_3 221 in_cell - unconnected 71 out_cell - lddata_4 222 in_cell - efbwen_1 72 out_cell - lddata_5 223 in_cell - oeb_efbwen_1 73 out_cell - lddata_6 224 in_cell - efbwdat_1 74 out_cell - lddata_7 225 in_cell - oeb_efbwdat_1 75 out_cell - l77 226 in_cell - unconnected 76 out_cell - lrefclk 227 in_cell - unconnected 77 out_cell - tneg_tmfp_1 228 out_cell - unconnected 78 out_cell - oeb_tneg_tmfp_1 229 out_cell - unconnected 79 out_cell - tclk_1 230 out_cell - unconnected 80 out_cell - oeb_tclk_1 231 out_cell - unconnected 81 out_cell - tpos_tdat_1 232 out_cell - unconnected 82 out_cell - oeb_tpos_tdat_1 233 out_cell - unconnected 83 out_cell - ticlk_1 234 in_cell - unconnected 84 out_cell - rneg_rlcv_1 235 in_cell - unconnected 85 out_cell - rpos_rdat_1 236 in_cell - efbwen_2 86 out_cell - rclk_1 237 in_cell - oeb_efbwen_2 87 out_cell - tneg_tmfp_2 238 out_cell - efbwdat_2 88 out_cell - oeb_tneg_tmfp_2 239 out_cell - oeb_efbwdat_2 89 out_cell - tclk_2 240 out_cell -
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 146 pin/ enable bit # cell type id bit pin/ enable bit # cell type id bit unconnected 90 out_cell - oeb_tclk_2 241 out_cell - unconnected 91 out_cell - tpos_tdat_2 242 out_cell - unconnected 92 out_cell - oeb_tpos_tdat_2 243 out_cell - unconnected 93 out_cell - ticlk_2 244 in_cell - unconnected 94 out_cell - rneg_rlcv_2 245 in_cell - unconnected 95 out_cell - rpos_rdat_2 246 in_cell - unconnected 96 out_cell - rclk_2 247 in_cell - unconnected 97 out_cell - tneg_tmfp_3 248 out_cell - unconnected 98 out_cell - oeb_tneg_tmfp_3 249 out_cell - unconnected 99 out_cell - tclk_3 250 out_cell - efbwen_3 100 out_cell - oeb_tclk_3 251 out_cell - oeb_efbwen_3 101 out_cell - tpos_tdat_3 252 out_cell - efbwdat_3 102 out_cell - oeb_tpos_tdat_3 253 out_cell - oeb_efbwdat_3 103 out_cell - ticlk_3 254 in_cell - unconnected 104 out_cell - rneg_rlcv_3 255 in_cell - unconnected 105 out_cell - rpos_rdat_3 256 in_cell - unconnected 106 out_cell - rclk_3 257 in_cell - unconnected 107 out_cell - rgapclk_rsclk_1 258 out_cell - unconnected 108 out_cell - oeb_rgapclk_rsclk_1 259 out_cell - unconnected 109 out_cell - rdato_1 260 out_cell - unconnected 110 out_cell - oeb_rdato_1 261 out_cell - unconnected 111 out_cell - rovrhd_1 262 out_cell - unconnected 112 out_cell - oeb_rovrhd_1 263 out_cell - unconnected 113 out_cell - rfpo_rmfpo_1 264 out_cell - ctclk 114 in_cell - oeb_rfpo_rmfpo_1 265 out_cell - unconnected 115 in_cell - tfpo_tmfpo_ tgapclk_1 266 out_cell - unconnected 116 in_cell - oeb_tfpo_tmfpo_ tgapclk_1 267 out_cell - unconnected 117 in_cell - tfpi_tmfpi_1 268 in_cell - ifbwclk_1 118 in_cell - tdati_1 269 in_cell - ifbwdat_1 119 in_cell - rgapclk_rsclk_2 270 out_cell 1 ifbwen_1 120 in_cell - oeb_rgapclk_rsclk_2 271 out_cell 0
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 147 pin/ enable bit # cell type id bit pin/ enable bit # cell type id bit efbwclk_1 121 in_cell - rdato_2 272 out_cell 1 efbwdreq_1 122 in_cell - oeb_rdato_2 273 out_cell 1 unconnected 123 in_cell - rovrhd_2 274 out_cell 0 unconnected 124 in_cell - oeb_rovrhd_2 275 out_cell 0 ifbwclk_2 125 in_cell - rfpo_rmfpo_2 276 out_cell 1 ifbwdat_2 126 in_cell - oeb_rfpo_rmfpo_2 277 out_cell 1 ifbwen_2 127 in_cell - tfpo_tmfpo_tgapclk_ 2 278 out_cell 0 efbwclk_2 128 in_cell - oeb_tfpo_tmfpo_ tgapclk_2 279 out_cell 0 efbwdreq_2 129 in_cell - tfpi_tmfpi_2 280 in_cell 0 unconnected 130 in_cell - tdati_2 281 in_cell 0 unconnected 131 in_cell - rgapclk_rsclk_3 282 out_cell 0 ifbwclk_3 132 in_cell - oeb_rgapclk_rsclk_3 283 out_cell 1 ifbwdat_3 133 in_cell - rdato_3 284 out_cell 1 ifbwen_3 134 in_cell - oeb_rdato_3 285 out_cell 0 efbwclk_3 135 in_cell - rovrhd_3 286 out_cell 1 efbwdreq_3 136 in_cell - oeb_rovrhd_3 287 out_cell 0 unconnected 137 in_cell - rfpo_rmfpo_3 288 out_cell 0 unconnected 138 in_cell - oeb_rfpo_rmfpo_3 289 out_cell 0 unconnected 139 in_cell - tfpo_tmfpo_ tgapclk_3 290 out_cell 1 unconnected 140 in_cell - oeb_tfpo_tmfpo_ tgapclk_3 291 out_cell 1 unconnected 141 in_cell - tfpi_tmfpi_3 292 in_cell 0 intb 142 out_cell - tdati_3 293 in_cell 0 oeb_intb 143 out_cell - recvclk_3 294 out_cell 0 d_0 144 io_cell - oeb_recvclk_3 295 out_cell 0 oeb_d_0 145 out_cell - recvclk_2 296 out_cell 0 d_1 146 io_cell - oeb_recvclk_2 297 out_cell 1 oeb_d_1 147 out_cell - recvclk_1 298 out_cell 0 d_2 148 io_cell - oeb_recvclk_1 299 out_cell 0 oeb_d_2 149 out_cell - xclk_e1 300 in_cell 0
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 148 pin/ enable bit # cell type id bit pin/ enable bit # cell type id bit d_3 150 io_cell - xclk_t1 301 in_cell 0 notes: 1. register bit 301 is the first bit of the scan chain (closest to tdi). 2. enable cell oeb_pinname, sets ball pinname to high-impedance when set high. 3. unconnected register bits in the scan chain are not connected to any pins.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 149 12 operation 12.1 tributary indexing the temux-84 is capable of transporting 84 1.544 mbit/s (t1) or 63 2.048 mbit/s (e1) tributaries. this section explains the correspondence between the indexing systems of the various mapping and multiplexing formats: sbi bus, telecom bus and m13. the listed index systems are used throughout the document. the sbi bus tributary designation uses two integers: the first represents the byte interleaved spe number (range 1 to 3) and the second is the link index within the spe (range 1 to 28). the telecom bus indexing follows the conventions of the itu-t multiplexing structure. the bandwidth is divided into three tug-3s numbered 1 through 3, each of which is composed of seven tug-2s numbered 1 through 7, each of which is composed of either three tu-12s numbered 1 through 3 or four tu-11s numbered 1 through 4. the three ds3s are divided into seven ds2s, each of which is composed of either four 1.544 mbit/s or three 2.048 mbit/s tributaries. the payload capacity is divided into three equal portions. each of the following lists represents one set of equivalent tributaries: ? spe #1, tug-3 #1 and ds3 #1 ? spe #2, tug-3 #2 and ds3 #2 ? spe #3, tug-3 #3 and ds3 #3 table 13 and table 14 provide the equivalencies between the various multiplex and mapping formats. alternately, the formats can be equated with the following formulae: 1.544mbit/s sbi link # = 7*(tu11-1) + tug2 = 4*(ds2-1)+ds1 2.048mbit/s sbi link # = 7*(tu12-1) + tug2 = 3*(ds2-1)+e1
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 150 table 13 - indexing for 1.544 mbit/s tributaries sbi bus spe, link telecom bus tug-3, tug-2, tu11 m13 ds3, ds2, ds1 1,1 1,1,1 1,1,1 1,2 1,2,1 1,1,2 1,3 1,3,1 1,1,3 1,4 1,4,1 1,1,4 1,5 1,5,1 1,2,1 1,6 1,6,1 1,2,2 1,7 1,7,1 1,2,3 1,8 1,1,2 1,2,4 1,9 1,2,2 1,3,1 1,10 1,3,2 1,3,2 1,11 1,4,2 1,3,3 1,12 1,5,2 1,3,4 1,13 1,6,2 1,4,1 1,14 1,7,2 1,4,2 1,15 1,1,3 1,4,3 1,16 1,2,3 1,4,4 1,17 1,3,3 1,5,1 1,18 1,4,3 1,5,2 1,19 1,5,3 1,5,3 1,20 1,6,3 1,5,4 1,21 1,7,3 1,6,1 1,22 1,1,4 1,6,2 1,23 1,2,4 1,6,3 1,24 1,3,4 1,6,4 1,25 1,4,4 1,7,1 1,26 1,5,4 1,7,2 1,27 1,6,4 1,7,3 1,28 1,7,4 1,7,4 2,1 2,1,1 2,1,1 ... ... ...
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 151 table 14 - indexing for 2.048 mbit/s tributaries sbi bus spe, link telecom bus tug-3, tug-2, tu12 m13 ds3, ds2, e1 1,1 1,1,1 1,1,1 1,2 1,2,1 1,1,2 1,3 1,3,1 1,1,3 1,4 1,4,1 1,2,1 1,5 1,5,1 1,2,2 1,6 1,6,1 1,2,3 1,7 1,7,1 1,3,1 1,8 1,1,2 1,3,2 1,9 1,2,2 1,3,3 1,10 1,3,2 1,4,1 1,11 1,4,2 1,4,2 1,12 1,5,2 1,4,3 1,13 1,6,2 1,5,1 1,14 1,7,2 1,5,2 1,15 1,1,3 1,5,3 1,16 1,2,3 1,6,1 1,17 1,3,3 1,6,2 1,18 1,4,3 1,6,3 1,19 1,5,3 1,7,1 1,20 1,6,3 1,7,2 1,21 1,7,3 1,7,3 2,1 2,1,1 2,1,1 ... ... ... 12.2 clock and frame synchronization constraints depending on the modes of operation utilized, some coordination between lrefclk, srefclk, lac1, ldc1j1v1, sdc1fp and sac1fp is required. specifically, tighter constraints must be respected when supporting transparent virtual tributaries (tvts) or 77.76 mhz buses. the following only applies when using the telecom bus. lrefclk may be tied low when support is limited to ds3/e3 serial line interfaces. 12.2.1 sbi and telecom buses both 19.44 mhz the rising and falling edges of lrefclk must be aligned with a tolerance of +/- 10ns to the corresponding edges of srefclk.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 152 restrictions on frame alignment pulses only exist when tvts are supported. the nature of the constraints depends on whether the vt pointer processors (vtpps) are bypassed: ? if the egress vtpp is bypassed, the sac1fp pulse must be precisely 13 srefclk cycles before the lac1 pulse. ? if the egress vtpp is not bypassed, the sac1fp pulse must be 3n - 1 (where n = 0,1,2?) srefclk cycles before the lac1 pulse. ? if the ingress vtpp is bypassed, the ldc1j1v1 pulse must be precisely four srefclk cycles before the sdc1fp pulse. ? if the ingress vtpp is not bypassed, there is no restriction on the alignment of sdc1fp and ldc1j1v1. 12.2.2 sbi and telecom buses both 77.76 mhz the rising edge of lrefclk must be aligned with a tolerance of +/- 5ns to the rising edge of srefclk. for reliable operation, the stm-1s used within the sbi and telecom buses must be aligned in time. to this end, one may manipulate the lstm[1:0] and sstm[1:0] register bits and the position of the lac1 and sdc1fp pulses. table 15 summarizes the combinations. table 15 - 77.76 sbi and telecom bus alignment options clock cycles lac1 leads sdc1fp (n = 0, 1 , 2?) lstm[1:0] sstm[1:0] 00 01 10 11 00 4n. 4n + 1 4n + 2 4n + 3 01 4n + 3 4n 4n + 1 4n + 2 10 4n + 2 4n + 3 4n 4n + 1 11 4n + 1 4n + 2 4n + 3 4n as an alternate formulation, if sstm[1:0] and lstm[1:0] were converted to their decimal equivalents, one would have to satisfy the constraint: (lstm ? sstm) mod 4 = (clock cycles lac1 leads sdc1fp) mod 4
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 153 12.2.3 19.44 mhz sbi bus and 77.76 mhz telecom bus the rising edge of lrefclk must be aligned with a tolerance of +/- 5ns to the rising edge of srefclk. for reliable operation, the stm-1s used within the telecom bus must be aligned to the srefclk input. to this end, one may manipulate the lstm[1:0] register bits and the position of the lac1 pulses. table 15 summarizes the combinations. table 16 - 19.44 mhz sbi to 77.76 mhz telecom to bus alignment options lstm[1:0] lrefclk cycles lac1 sampling edge leads srefclk rising edge 00 1 01 2 10 3 11 0 as alternate formulation, if lstm[1:0] was converted to its decimal equivalent, one would have to satisfy the constraint: (lstm + 1) mod 4 = clock cycles lac1 leads srefclk 12.2.4 77.76 mhz sbi bus and 19.44 mhz telecom bus the rising edge of lrefclk must be aligned with a tolerance of +/- 5ns to the rising edge of srefclk. for reliable operation, the stm-1s used within the sbi bus must be aligned to lrefclk. to this end, one may manipulate the sstm[1:0] register bits and the position of the sdc1fp pulses. table 15 summarizes the combinations. table 17 - 77.76 mhz sbi to 19.44 mhz telecom to bus alignment options sstm[1:0] srefclk cycles sdc1fp sampling edge leads lrefclk rising edge 00 1
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 154 01 2 10 3 11 0 as alternate formulation, if sstm[1:0] was converted to its decimal equivalent, one would have to satisfy the constraint: (sstm + 1) mod 4 = clock cycles sdc1fp leads lrefclk 12.3 ds3 frame format the temap-84 provides support for both the c-bit parity and m23 ds3 framing formats. the ds3 frame format is shown in figure 13. figure 12 - ds3 frame structure x 1 f 1 c 1 f 2 c 2 f 3 f 4 c 3 x 2 f 1 c 1 f 2 c 2 f 3 f 4 c 3 p 1 f 1 c 1 f 2 c 2 f 3 f 4 c 3 p 2 f 1 c 1 f 2 c 2 f 3 f 4 c 3 m 1 f 1 c 1 f 2 c 2 f 3 f 4 c 3 m 2 f 1 c 1 f 2 c 2 f 3 f 4 c 3 m 3 f 1 c 1 f 2 c 2 f 3 f 4 c 3 84 bits 84 bits 84 bits 84 bits 84 bits 84 bits 84 bits 84 bits m-subframe 1 m-subframe 7 m-subframe 6 m-subframe 5 m-subframe 4 m-subframe 3 m-subframe 2 x x : x-bit channel ? transmit: the temap-84 inserts the ferf signal on the x-bits. ferf generation is controlled by either the ferf bit of the ds3 tran configuration register or by detection of oof, red, los and ais, as configured by the temap-84 master ds3 alarm enable register. ? receive: the temap-84 monitors the state and detects changes in the state of the ferf signal on the x-bits. p x : p-bit channel ? transmit: the temap-84 calculates the parity for the payload data over the previous m-frame and inserts it into the p1 and p2 bit positions. ? receive: the temap-84 calculates the parity for the received payload. errors are accumulated in the ds3 pmon parity error event count registers.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 155 m x : m-frame alignment signal ? transmit: the temap-84 generates the m-frame alignment signal (m1 = 0, m2 = 1, m3 = 0). ? receive: the temap-84 finds m-frame alignment by searching for the f- bits and the m-bits. out-of-frame is removed if the m-bits are correct for three consecutive m-frames while no discrepancies have occurred in the f- bits. m-bit errors are counted in the ds3 pmon framing bit error event count registers. when one or more m-bit errors are detected in 3 out of 4 consecutive m-frames, an out-of-frame defect is asserted (if mbdis in the ds3 framer configuration register is a logic 0). f x : m-subframe alignment signal ? transmit: the temap-84 generates the m-subframe alignment signal (f1=1, f2=0, f3=0, f4=1). ? receive: the temap-84 finds m-frame alignment by searching for the f- bits and the m-bits. out-of-frame is removed if the m-bits are correct for three consecutive m-frames while no discrepancies have occurred in the f- bits. f-bit errors are counted in the ds3 pmon framing bit error event count registers. an out-of frame defect is asserted if 3 f-bit errors out of 8 or 16 consecutive f-bits are observed (as selected by the m3o8 bit in the ds3 frmr configuration register). c x : c-bit channels ? transmit: when configured for m23 applications, the c-bits used for stuffing indication. when configured for c-bit parity applications, the c-bit parity id bit is forced to logic 1. the second c-bit in m-subframe 1 is set to logic 1. the third c-bit in m-subframe 1 provides a far-end alarm and control (feac) signal. the feac channel is sourced by the ds3 xboc block. the 3 c-bits in m-subframe 3 carry path parity information. the value of these 3 c-bits is the same as that of the p-bits. the 3 c-bits in m- subframe 4 are the febe bits. febe transmission is controlled by the dfebe bit in the ds3 tran diagnostic register and by the detection of receive framing bit and path parity errors. the 3 c-bits in m-subframe 5 contain the 28.2 kbit/s path maintenance datalink. these bits are inserted from the ds3 tdpr hdlc controller. the c-bits in m-subframes 2, 6, and 7 are unused and are set to logic 1. ? receive: the cbitv register bit in the ds3 frmr status register is used to report the state of the c-bit parity id bit, and hence whether a m23 or c- bit parity ds3 signal stream is being received. the feac channel on the third c-bit in m-subframe 1 is detected by the ds3 rboc block. path parity errors and detected febes on the c-bits in m-subframes 3 and 4 are reported in the ds3 pmon path parity error event count and febe event
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 156 count registers respectively. the path maintenance datalink signal is extracted by theds3 rdlc hdlc receiver (if enabled). 12.4 servicing interrupts the temap-84 will assert intb to logic 0 when a condition which is configured to produce an interrupt occurs. to find which condition caused this interrupt to occur, the procedure outlined below should be followed: 1. read the bits of the temap-84 master interrupt source register (0x0010) to identify which of the 14 interrupt registers (0x0011-0x001e) needs to be read to identify the interrupt. for example, a logic one read in the ds3e3int register bit indicates that an interrupt identified in one of the three master interrupt source ds3/e3 registers produced the interrupt. 2. read the bits of the second level master interrupt source register to identify the interrupt source. 3. service the interrupt by reading the register containing the interrupt status bit that is asserted. 4. if the intb pin is still logic 0, then there are still interrupts to be serviced. otherwise, all interrupts have been serviced. wait for the next assertion of intb 12.5 using the performance monitoring features the counters in the ds3 pmon block has been sized as not to saturate if polled every second. the t1/e1 pmon event counters are of sufficient length so that the probability of counter saturation over a one second interval is very small (less than 0.001%). an accumulation interval is initiated by writing to one of the pmon event counter register addresses or by writing to the global pmon update register. after initiating an accumulation interval, 3.5 recovered clock periods (rclk for the ds3 pmon) must be allowed to elapse to permit the pmon counter values to be properly transferred before the pmon registers may be read. the odds of any one of the t1/e1 counters saturating during a one second sampling interval go up as the bit error rate (ber) increases. at some point, the probability of counter saturation reaches 50%. this point varies, depending upon the framing format and the type of event being counted. the ber at which the probability of counter saturation reaches 50% is shown for various counters in table 18 for e1 mode, and in table 19 for t1 mode.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 157 table 18 - pmon counter saturation limits (e1 mode) counter ber fer 4.0 x 10 -3 crce cannot saturate febe cannot saturate table 19 - pmon counter saturation limits (t1 mode) counter format ber fer sf 1.6 x 10 -3 esf 6.4 x 10 -2 crce sf 1.28 x 10 -1 esf cannot saturate below these 50% points, the relationship between the ber and the counter event count (averaged over many one second samples) is essentially linear. above the 50% point, the relationship between ber and the average counter event count is highly non-linear due to the likelihood of counter saturation. the following figures show this relationship for various counters and framing formats. these graphs can be used to determine the ber, given the average event count. in general, if the ber is above 10 -3 , the average counter event count cannot be used to determine the ber without considering the statistical effect of occasional counter saturation. figure 13 illustrates the expected count values for a range of bit error ratios in e1 mode.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 158 figure 13 - fer count vs. ber (e1 mode) 0 50 100 150 200 250 0 1 2 3 4 5 6 7 8 9 average count over many 1 second intervals bit error rate (x 10 ) -3 framing bit error count per second since the maximum number of crc sub-multiframes that can occur in one second is 1000, the 10-bit febe and crce counters cannot saturate in one second. despite this, there is not a linear relationship between ber and crc-4 block errors due to the nature of the crc-4 calculation. at bers below 10 -4 , there tends to be no more than one bit error per sub-multiframe, so the number of crc-4 errors is generally equal to the number of bit errors, which is directly related to the ber. however, at bers above 10 -4 , each crc-4 error is often due to more than one bit error. thus, the relationship between ber and crce count becomes non-linear above a 10 -4 ber. this must be taken into account when using crc-4 counts to determine the ber. since febes are indications of crces at the far end, and are accumulated identically to crces, the same explanation holds for the febe event counter. the bit error rate for e1 can be calculated from the one-second pmon crce count by the following equation: bit error rate = 1 - 10 ? 256 * 8 8000 8 1 log crce
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 159 figure 14 - crce count vs. ber (e1 mode) 1.00e-07 1.00e-06 1.00e-05 1.00e-04 1.00e-03 1.00e-02 0 200 400 600 800 1000 1200 crce bit error rate figure 15 illustrates the expected count values for a range of bit error ratios in t1 mode. figure 15 - fer count vs. ber (t1 esf mode) 0 50 100 150 200 250 0 1 2 3 4 5 6 7 8 9 average count over many 1 second intervals b i t e r r o r r a t e ( x 1 0 ) - 2 framing bit error count per second since the maximum number of esf superframes that can occur in one second is 333, the 9-bit bee counter cannot saturate in one second in esf framing format. despite this, there is not a linear relationship between ber and bee count, due to the nature of the crc-6 calculation. at bers below 10 -4 , there tends to be no more than one bit error per superframe, so the number of crc-6 errors is generally equal to the number of bit errors, which is directly related to the ber. however, at bers above 10 -4 , each crc-6 error is often due to more than one bit error. thus, the relationship between ber and bee count becomes non- linear above a 10 -4 ber. this must be taken into account when using esf crc-6 counts to determine the ber.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 160 the bit error rate for t1 esf can be calculated from the one-second pmon crce count by the following equation: bit error rate = 1 - 10 ? 193 * 24 8000 24 1 log bee figure 16 - crce count vs. ber (t1 esf mode) 1.00e-07 1.00e-06 1.00e-05 1.00e-04 1.00e-03 1.00e-02 0 50 100 150 200 250 300 350 crce bit error rate for t1 sf format, the crce and fer counts are identical, but the fer counter is smaller and should be ignored. figure 17 - crce count vs. ber (t1 sf mode) 0 2 4 6 8 10 12 14 16 0 200 400 600 800 1000 1200 bit error event count per second b i t e r r o r r a t e ( x 1 0 ) - 2 average count over many 1 second intervals 18 20 12.6 using the internal ds3 or e3 hdlc transmitter it is important to note that access rate to the tdpr registers is limited by the rate of the internal ds3/e3 clock. consecutive accesses to the tdpr configuration, tdpr interrupt status/udr clear, and tdpr transmit data register should be
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 161 accessed (with respect to wrb rising edge and rdb falling edge) at a rate no faster than 1/8 that of the ds3 or e3 clock. this time is used by the high-speed system clock to sample the event, write the fifo, and update the fifo status. instantaneous variations in the high-speed reference clock frequencies (e.g. jitter in the line clock) must be considered when determining the procedure used to read and write the tdpr registers. upon reset of the temap-84, the tdpr should be disabled by setting the en bit in the tdpr configuration register to logic 0 (default value). an hdlc all-ones idle signal will be sent while in this state. the tdpr is enabled by setting the en bit to logic 1. the fifoclr bit should be set and then cleared to initialize the tdpr fifo. the tdpr is now ready to transmit. to initialize the tdpr, the tdpr configuration register must be properly set. if fcs generation is desired, the crc bit should be set to logic 1. if the block is to be used in interrupt driven mode, then interrupts should be enabled by setting the fulle, ovre, udre, and lfille bits in the tdpr interrupt enable register to logic 1. the tdpr operating parameters in the tdpr upper transmit threshold and tdpr lower interrupt threshold registers should be set to the desired values. the tdpr upper transmit threshold sets the value at which the tdpr automatically begins the transmission of hdlc packets, even if no complete packets are in the fifo. transmission will continue until the current packet is transmitted and the number of bytes in the tdpr fifo falls to, or below, this threshold level. the tdpr will always transmit all complete hdlc packets (packets with eom attached) in its fifo. finally, the tdpr can be enabled by setting the en bit to logic 1. if no message is sent after the en bit is set to logic 1, continuous flags will be sent. the tdpr can be used in a polled or interrupt driven mode for the transfer of data. in the polled mode the processor controlling the tdpr must periodically read the tdpr interrupt status register to determine when to write to the tdpr transmit data register. in the interrupt driven mode, the processor controlling the tdpr uses the intb output, the one of the temap-84 master interrupt source registers, and the temap-84 tdpr interrupt status registers to identify tdpr interrupts which determine when writes can or must be done to the tdpr transmit data register. interrupt driven mode: the tdpr automatically transmits a packet once it is completely written into the tdpr fifo. the tdpr also begins transmission of bytes once the fifo level exceeds the programmable upper transmit threshold. the crc bit can be set to logic 1 so that the fcs is generated and inserted at the end of a packet. the tdpr lower interrupt threshold should be set to such a value that sufficient
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 162 warning of an underrun is given. the fulle, lfille, ovre, and udre bits are all set to logic 1 so an interrupt on intb is generated upon detection of a fifo full state, a fifo depth below the lower limit threshold, a fifo overrun, or a fifo underrun. the following procedure should be followed to transmit hdlc packets: 1. wait for a complete packet to be transmitted. once data is available to be transmitted, then go to step 2. 2. write the data byte to the tdpr transmit data register. 3. if all bytes of the packet have been written to the transmit data register, then set the eom bit in the tdpr configuration register to logic 1. go to step 1. 4. if there are more bytes in the packet to be sent, then go to step 2. while performing steps 1 to 4, the processor should monitor for interrupts generated by the tdpr. when an interrupt is detected, the tdpr interrupt routine detailed in the following text should be followed immediately. the tdpr will force transmission of the packet information when the fifo depth exceeds the threshold programmed with the uthr[6:0] bits in the tdpr upper transmit threshold register. unless an error condition occurs, transmission will not stop until the last byte of all complete packets is transmitted and the fifo depth is at or below the threshold limit. the user should watch the fulli and lfilli interrupts to prevent overruns and underruns. tdpr interrupt routine: upon assertion of intb, the source of the interrupt must first be identified by reading the temap-84 master interrupt source register (0020h) followed by reading one of the second level master interrupt source registers t1e1int1, t1e1int2, t1e1int3, t1e1int4 or ds3int. once the source of the interrupt has been identified as the tdpr in use, then the following procedure should be carried out: 1. read the tdpr interrupt status register. 2. if udri=1, then the fifo has underrun and the last packet transmitted has been corrupted and needs to be retransmitted. when the udri bit transitions to logic 1, one abort sequence and continuous flags will be transmitted. the tdpr fifo is held in reset state. to re-enable the tdpr fifo and to clear the underrun, the tdpr interrupt status/udr clear register should be written with any value.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 163 3. if ovri=1, then the fifo has overflowed. the packet of which the last byte written into the fifo belongs to, has been corrupted and must be retransmitted. other packets in the fifo are not affected. either a timer can be used to determine when sufficient bytes are available in the fifo or the user can wait until the lfilli interrupt is set, indicating that the fifo depth is at the lower threshold limit. if the fifo overflows on the packet currently being transmitted (packet is greater than 128 bytes long), ovri is set, an abort signal is scheduled to be transmitted, the fifo is emptied, and then flags are continuously sent until there is data to be transmitted. the fifo is held in reset until a write to the tdpr transmit data register occurs. this write contains the first byte of the next packet to be transmitted. 4. if fulli=1 and full=1, then the tdpr fifo is full and no further bytes can be written. when in this state, either a timer can be used to determine when sufficient bytes are available in the fifo or the user can wait until the lfilli interrupt is set, indicating that the fifo depth is at the lower threshold limit. if fulli=1 and full=0, then the tdpr fifo had reached the full state earlier, but has since emptied out some of its data bytes and now has space available in its fifo for more data. 5. if lfilli=1 and blfill=1, then the tdpr fifo depth is below its lower threshold limit. if there is more data to transmit, then it should be written to the tdpr transmit data register before an underrun occurs. if there is no more data to transmit, then an eom should be set at the end of the last packet byte. flags will then be transmitted once the last packet has been transmitted. if lfilli=1 and blfill=0, then the tdpr fifo had fallen below the lower- threshold state earlier, but has since been refilled to a level above the lower- threshold level. polling mode: the tdpr automatically transmits a packet once it is completely written into the tdpr fifo. the tdpr also begins transmission of bytes once the fifo level exceeds the programmable upper transmit threshold. the crc bit can be set to logic 1 so that the fcs is generated and inserted at the end of a packet. the tdpr lower interrupt threshold should be set to such a value that sufficient warning of an underrun is given. the fulle, lfille, ovre, and udre bits are all set to logic 0 since packet transmission is set to work with a periodic polling procedure. the following procedure should be followed to transmit hdlc packets:
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 164 1. wait until data is available to be transmitted, then go to step 2. 2. read the tdpr interrupt status register. 3. if full=1, then the tdpr fifo is full and no further bytes can be written. continue polling the tdpr interrupt status register until either full=0 or blfill=1. then, go to either step 4 or 5 depending on implementation preference. 4. if blfill=1, then the tdpr fifo depth is below its lower threshold limit. write the data into the tdpr transmit data register. go to step 6. 5. if full=0, then the tdpr fifo has room for at least 1 more byte to be written. write the data into the tdpr transmit data register. go to step 6. 6. if more data bytes are to be transmitted in the packet, then go to step 2. if all bytes in the packet have been sent, then set the eom bit in the tdpr configuration register to logic 1. go to step 1. 12.7 using the internal ds3 or e3 data link receiver it is important to note that the access rate to the rdlc registers is limited by the rate of the internal ds3 or e3 clock. consecutive accesses to the rdlc status and rdlc data registers should be accessed at a rate no faster than 1/10 that of the selected rdlc high-speed system clock. this time is used by the high- speed system clock to sample the event and update the fifo status. instantaneous variations in the ds3 or e3 frequencies (e.g. jitter in the receive line clock) must be considered when determining the procedure used to read rdlc registers. on power up of the system, the rdlc should be disabled by setting the en bit in the configuration register to logic 0 (default state). the rdlc interrupt control register should then be initialized to enable the intb output and to select the fifo buffer fill level at which an interrupt will be generated. if the inte bit is not set to logic 1, the rdlc status register must be continuously polled to check the interrupt status (intr) bit. after the rdlc interrupt control register has been written, the rdlc can be enabled at any time by setting the en bit in the rdlc configuration register to logic 1. when the rdlc is enabled, it will assume the link status is idle (all ones) and immediately begin searching for flags. when the first flag is found, an interrupt will be generated, and a dummy byte will be written into the fifo buffer. this is done to provide alignment of link up status with the data read from the fifo. when an abort character is received, another dummy byte and link down
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 165 status is written into the fifo. this is done to provide alignment of link down status with the data read from the fifo. it is up to the controlling processor to check the cols bit in the rdlc status register for a change in the link status. if the cols bit is set to logic 1, the fifo must be emptied to determine the current link status. the first flag and abort status encoded in the pbs bits is used to set and clear a link active software flag. when the last byte of a properly terminated packet is received, an interrupt is generated. while the rdlc status register is being read the pkin bit will be logic 1. this can be a signal to the external processor to empty the bytes remaining in the fifo or to just increment a number-of-packets-received count and wait for the fifo to fill to a programmable level. once the rdlc status register is read, the pkin bit is cleared to logic 0 . if the rdlc status register is read immediately after the last packet byte is read from the fifo, the pbs[2] bit will be logic 1 and the crc and non-integer byte status can be checked by reading the pbs[1:0] bits. when the fifo fill level is exceeded, an interrupt is generated. the fifo must be emptied to remove this source of interrupt. the rdlc can be used in a polled or interrupt driven mode for the transfer of frame data. in the polled mode, the processor controlling the rdlc must periodically read the rdlc status register to determine when to read the rdlc data register. in the interrupt driven mode, the processor controlling the rdlc uses the temap-84 intb output and the temap-84 master interrupt source registers to determine when to read the rdlc data register. in the case of interrupt driven data transfer from the rdlc to the processor, the intb output of the temap-84 is connected to the interrupt input of the processor. the processor interrupt service routine verifies what block generated the interrupt by reading the temap-84 master interrupt source register followed by one of the second level master interrupt source registers to identify one of the 3 hdlc receivers as the interrupt source. once it has identified that the rdlc has generated the interrupt, it processes the data in the following order: 1. read the rdlc status register. the intr bit should be logic 1. 2. if ovr = 1, then discard the last frame and go to step 1. overrun causes a reset of fifo pointers. any packets that may have been in the fifo are lost. 3. if cols = 1, then set the empty fifo software flag. 4. if pkin = 1, increment the packet count. if the fifo is desired to be emptied as soon as a complete packet is received, set the empty fifo
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 166 software flag. if the empty fifo software flag is not set, fifo emptying will delayed until the fifo fill level is exceeded. 5. read the rdlc data register. 6. read the rdlc status register. 7. if ovr = 1, then discard last frame and go to step 1. overrun causes a reset of fifo pointers. any packets that may have been in the fifo are lost. 8. if cols = 1, then set the empty fifo software flag. 9. if pkin = 1, increment the packet count. if the fifo is desired to be emptied as soon as a complete packet is received, set the empty fifo software flag. if the empty fifo software flag is not set, fifo emptying will delayed until the fifo fill level is exceeded. 10. start the processing of fifo data. use the pbs[2:0] packet byte status bits to decide what is to be done with the fifo data. if pbs[2:0] = 001, discard data byte read in step 5 and set the link active software flag. if pbs[2:0] = 010, discard the data byte read in step 5 and clear the link active software flag. if pbs[2:0] = 1xx, store the last byte of the packet, decrement the packet count, and check the pbs[1:0] bits for crc or nvb errors before deciding whether or not to keep the packet. if pbs[2:0] = 000, store the packet data. 11. if fe = 0 and intr = 1 or fe = 0 and empty fifo = 1, go to step 5 else clear the empty fifo software flag and leave this interrupt service routine to wait for the next interrupt. the link state is typically a local software variable. the link state is inactive if the rdlc is receiving all ones or receiving bit-oriented codes which contain a sequence of eight ones. the link state is active if the rdlc is receiving flags or data. if the rdlc data transfer is operating in the polled mode, processor operation is exactly as shown above for the interrupt driven mode, except that the entry to the service routine is from a timer, rather than an interrupt.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 167 figure 18 - typical data frame 87654321 01111110 flag address (high) (low) control frame check sequence 01111110 flag data bytes received and transferred to the fifo buffer bit: bit 1 is the first serial bit to be received. when enabled, the primary, secondary and universal addresses are compared with the high order packet address to determine a match. figure 19 - example multi-packet operational sequence data int fe la 12 345 67 f f f fa d d d dd d d d d ddddd f f f fd d d dff f - flag sequence (0 1111110) a - abort sequence (0 1111111) d - packet data bytes int - active high interrupt output fe - internal fifo empty status la - state of the link active software flag figure 19 shows the timing of interrupts, the state of the fifo, and the state of the data link relative the input data sequence. the cause of each interrupt and
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 168 the processing required at each point is described in the following paragraphs. the actual interrupt signal, intb, is active low and will be the inverse of the int signal shown in figure 19. also in this example, the programmable fill level set point is set at 8 bytes by writing this value into the intc[6:0] bits of the rdlc interrupt control register. at points 1 and 5 the first flag after all ones or abort is detected. a dummy byte is written in the fifo, fe goes low, and an interrupt goes active. when the interrupt is detected by the processor it reads the dummy byte, the fifo becomes empty, and the interrupt is removed. the link active (la) software flag is set to logic 1. at points 2 and 6 the last byte of a packet is detected and interrupt goes high. when the interrupt is detected by the processor, it reads the data and status registers until the fifo becomes empty. the interrupt is removed as soon as the rdlc status register is read, since the fifo fill level of 8 bytes has not been exceeded. it is possible to store many packets in the fifo and empty the fifo when the fifo fill level is exceeded. in either case the processor should use this interrupt to count the number of packets written into the fifo. the packet count or a software time-out can be used as a signal to empty the fifo. at point 3 the fifo fill level of 8 bytes is exceeded and interrupt goes high. when the interrupt is detected by the processor it must read the data and status registers until the fifo becomes empty and the interrupt is removed. at points 4 or 7 an abort character is detected, a dummy byte is written into the fifo, and interrupt goes high. when the interrupt is detected by the processor it must read the data and status registers until the fifo becomes empty and the interrupt is removed. the link active software flag is cleared. 12.8 t1/e1 loopback modes the temap-84 provides two loopback modes for t1/e1 links to aid in network and system diagnostics. the internal t1/e1 line loopback can be initiated at any time via the p interface, but is usually initiated once an inband loopback activate code is detected. the system diagnostic digital loopback can be initiated at any time by the system via the p interface to check the path of system data through the framer. t1/e1 line loopback t1/e1 line loopback is initiated by setting the lloop bit to a 1 through the tjat indirect channel data register. when in line loopback mode, the appropriate tributary in the temap-84 is configured to internally connect the jitter-attenuated
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 169 clock and data from the rjat to the transmit clock and data going to the m13 mux and sonet/sdh mapper. the rjat may be bypassed if desired. conceptually, the data flow through a single tributary in this loopback condition is illustrated in figure 20. figure 20 - t1/e1 line loopback t1/e1 jat84 ttmp (bit) rtdm (bit) m13 m13 m13 m13 m13 m13 m13 m13 ds3/e3 frmr m13 m13 ds3/e3 tran trap m13 m13 vtpp m13 m13 vtpp m13 m13 sipo m13 m13 piso m13 m13 d3ma m13 m13 d3md telecom bus telecom bus lius lius sbi 155 ttop m13 m13 rtop/ rttb t1/e1 jat84 exsbi insbi insbi (byte) exsbi (byte) egress flexible b/w port ingress flexible b/w port ds3/e3 tx system i/f ds3/e3 rx system i/f t1/e1 frmr84 line loopback t1/e1 diagnostic digital loopback when diagnostic digital loopback is initiated, by writing a 1 to the dloop bit through the rjat indirect channel data register, the appropriate tributary in the temap-84 is configured to internally connect its transmit clock and data to the receive clock and data the data flow through a single tributary in this loopback condition is illustrated in figure 21.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 170 figure 21 - t1/e1 diagnostic digital loopback t1/e1 jat84 ttmp (bit) rtdm (bit) m13 m13 m13 m13 m13 m13 m13 m13 ds3/e3 frmr m13 m13 ds3/e3 tran trap m13 m13 vtpp m13 m13 vtpp m13 m13 sipo m13 m13 piso m13 m13 d3ma m13 m13 d3md telecom bus telecom bus lius lius sbi 155 ttop m13 m13 rtop/ rttb t1/e1 jat84 exsbi insbi insbi (byte) exsbi (byte) egress flexible b/w port ingress flexible b/w port ds3/e3 tx system i/f ds3/e3 rx system i/f t1/e1 frmr84 diagnostic loopback 12.9 ds3 and e3 loopback modes the temap-84 provides two e3 and three ds3 m13 multiplexer loopback modes to aid in network and system diagnostics at the ds3 interface. the ds3 loopbacks can be initiated via the p interface whenever the ds3 framer/m13 multiplexer is enabled. the ds3 and e3 master data source register controls the ds3 loopback modes. these loopbacks are also available when the ds3 mux is used with the ds3 mapper via the telecom bus interface. ds3 and e3 diagnostic loopback ds3 and e3 diagnostic loopback allows the transmitted ds3 or e3 stream to be looped back into the receive ds3 or e3 path, overriding the ds3 or e3 stream received on the rdat/rpos and rneg/rlcv inputs. the rclk signal is also substituted with the transmit ds3 clock, tclk. while this mode is active, ais may be substituted for the ds3 payload being transmitted on the tpos/tdat and tneg/tmfp outputs. the configuration of the receive interface determines how the tneg/tmfp signal is handled during loopback: if the uni bit in the ds3 frmr register is set, then the receive interface is configured for rdat and rlcv, therefore the tneg/tmfp signal is suppressed during loopback so that transmit mfp indications will not be seen nor accumulated as input lcvs. if the uni bit is clear, then the interface is configured for bipolar signals rpos and rneg, therefore the tneg is fed directly to the rneg input. this diagnostic
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 171 loopback can be used when configured as a multiplexer or as a framer only. the ds3 loopback mode is shown diagrammatically in figure 22. figure 22 - ds3 diagnostic loopback diagram ds3/e3 frmr ds3/e3 tran rclk rpos/ rdat rneg/ rlcv tclk tpos/ tdat tneg/ tmfp uni optional ais insertion ds3 and e3 line loopback ds3 and e3 line loopbacks allow the received ds3/e3 streams to be looped back into the transmit ds3/e3 paths, overriding the ds3/e3 streams created internally by the framing unchannelized data or multiplexing of the lower speed tributaries. the transmit signals on tpos/tdat and tneg/tmfp are substituted with the receive signals from rpos/rdat and rneg/rlcv. the tclk signal is also substituted with the receive ds3/e3 clock, rclk. while this mode is active, ais may be substituted for the ds3 payload being transmitted on the tpos/tdat and tneg/tmfp outputs. note that the transmit interface must be configured to be the same as the ds3/e3 frmr receive interface for this mode to work properly. the ds3/e3 line loopback mode is shown diagrammatically in figure 23. there is a second form of line loopback which only loops back the ds3/e3 payload. in this mode the ds3 framing overhead is regenerated for the received ds3/e3 stream and then retransmitted. line loopback is selected with the lloop bit in the ds3 and e3 master data source register and payload loopback is selected by the ploop bit in the same register.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 172 figure 23 - ds3 and e3 line loopback diagram ds3/e3 frmr ds3/e3 tran rclk rpos/ rdat rneg/ rlcv tclk tpos/ tdat tneg/ tmfp ds2 demultiplex loopback ds2 demultiplex loopbacks allow each of the seven demultiplexed ds2 streams to be looped back into the mx23 and multiplexed up into the transmit ds3 stream. this overrides the tributary ds2 streams coming from the mx12s. the ds2 loopback mode is shown diagrammatically in figure 24 and is enabled via the mx23 loopback activate register. figure 24 - ds2 loopback diagram mx12 #7 f r m r mx12 #6 f r m r mx12 #5 f r m r mx12 #4 f r m r mx12 #3 f r m r mx12 #2 f r m r ds3 frmr ds3 tran mx23 mx12 #1 f r m r rclk rpos/ rdat rneg/ rlcv tclk tpos/ tdat tneg/ tmfp optional demux ais insertion ds2 tributary loopback path
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 173 12.10 telecom bus mapper/demapper loopback modes the temap-84 provides two loopbacks at the telecom bus interface to aid in network and system diagnostics at the sonet/sdh interface. these loopback modes can be enabled via the microprocessor whenever the sonet/sdh block is enabled as the mapper for the t1/e1 framer slices or as the mapper for the ds3 framer or m13 multiplexer. telecom diagnostic loopback the telecom bus diagnostic loopback allows the transmitted telecom bus stream to be looped back into the receive sonet/sdh receive path, overriding the data stream received on the telecom drop bus inputs. while telecom diagnostic loopback is active, valid sonet/sdh data continues to be transmitted on the telecom add bus outputs. the entire telecom drop bus is overwritten by the diagnostic loopback even though only one sts-1 spe, stm- 1/vc4 tug3 or stm-1/vc3 is generated by the egress vtpp onto the telecom add bus. this loopback is only available for vt1.5/vt2/tu11/tu12 mapped tributaries. ds3 mapped tributaries must use the ds3 diagnostic loopback. the telecom bus diagnostic loopback mode is shown diagrammatically in figure 25. figure 25 - telecom diagnostic loopback diagram v tpp vt/tu payload processor v tpp vt/tu payload processor lddata[7:0] lddp ldpl ldc1j1 ladata[7:0] ladp lapl lac1j1v1 lac1 rtop receive tributary path o/h telecom line loopback the telecom bus line loopback allows the received telecom drop bus data to be looped back out the telecom add bus after being processed by both the ingress and egress vtpps. both vtpp must be setup for the same sts-1 spe,
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 174 stm-1/vc4 tug3 or stm-1/vc3 otherwise no loopback data will get through. the ingress data path is not affected by the telecom line loopback. this loopback is only available for vt1.5/vt2/tu11/tu12 mapped tributaries. ds3 mapped tributaries must use the ds3 line loopback. the telecom bus line loopback mode is shown diagrammatically in figure 26. figure 26 - telecom line loopback diagram vtpp vt/tu payload processor vtpp vt/tu payload processor lddata[7:0] lddp ldpl ldc1j1 ladata[7:0] ladp lapl lac1j1v1 la c 1 rtop receive tributary path o/h ttop transmit tributary path o/h 12.11 sbi bus data formats the temap-84 uses the scaleable bandwidth interconnect (sbi) bus as a high density link interconnect with devices processing t1s, e1s, ds3s, e3s, transparent virtual tributaries and arbitary bandwidth payloads. the sbi bus is a multi-point to multi-point bus capable of interconnecting up to four temap-84 devices in parallel (if connected to a 77.76 mhz bus) with other link layer or tributary processing devices. multiplexing structure the sbi structure uses a locked sonet/sdh structure fixing the position of the tu-3 relative to the sts-3/stm-1. the sbi is also of fixed frequency and alignment as determined by the reference clock (srefclk) and frame indicator signals (sac1fp and sdc1fp). frequency deviations are compensated by adjusting the location of the t1/e1/ds3/tvt1.5/tvt2 channels using floating tributaries as determined by the v5 indicator and payload signals (sdv5, sav5, sdpl and sapl). tvts also allow for synchronous operation where
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 175 sonet/sdh tributary pointers are carried within the sbi structure in place of the v5 indicator and payload signals (sdv5, sav5, sdpl and sapl). table 20 shows the bus structure for carrying t1, e1, tvt1.5, tvt2, ds3 and e3 tributaries in a sdh stm-1 like format. up to 84 t1s, 63 e1s, 84 tvt1.5s, 63 tvt2s, 3 ds3s or 3 e3s are carried within the octets labeled spe1, spe2 and spe3 in columns 16-270. all other octets are unused and are of fixed position. the frame signal (sac1fp or sdc1fp) occurs during the octet labeled c1 in row 1 column 7. the add and drop buses have independent frame signals to allow for arbitrary alignment of the two buses. table 20 represents a 19.44 mbit/s signal. the structure is presented on a 77.76 mhz bus by byte interleaving it with three other like structures. the multiplexed links are separated into three synchronous payload envelopes called spe1, spe2 and spe3. each envelope carries up to 28 t1s, 21 e1, 28 tvt1.5s, 21 tvt2s, a ds3 or an e3. spe1 carries the t1s numbered 1,1 through 1,28, e1s numbered 1,1 through 1,21, ds3 number 1,1 or e3 number 1,1. spe2 carries t1s numbered 2,1 through 2,28, e1s numbered 2,1 through 2,21, ds3 number 2,1 or e3 number 2,1. spe3 carries t1s numbered 3,1 through 3,28, e1s numbered 3,1 through 3,21, ds3 number 3,1 or e3 number 3,1. tvt1.5s are numbered the same as t1 tributaries and tvt2s are numbered the same as e1 tributaries.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 176 table 20 - structure for carrying multiplexed links sbi column 1 6 7 8 15 16 17 18 19 268 269 270 row 1 - ??? -c1- ??? - spe1spe2spe3spe1 ??? spe1spe2spe3 2- ??? --- ??? - spe1spe2spe3spe1 ??? spe1spe2spe3 9 - - - - - spe1spe2spe3spe1 spe1spe2spe3 1 233 56667 909090 spe column the temap-84 when enabled for sbi interconnection will add and drop either 28 t1s, 21 e1s, a ds3 or an e3 into each of the three synchronous payload envelopes, spe1, spe2 or spe3. each spe is independent of the others. when t1 or e1 tributaries are sourced from the telecom bus via vt1.5, tu11, vt2 or tu12 mappings, the temap-84 also supports a mix of transparent virtual tributaries with t1s and e1s. a restriction to this are that only vt1.5s, tu11s and t1s can be mixed together or vt2s, tu12s and e1s can be mixed together. another restriction is that the telecom bus and sbi bus must run from the same clock with a fixed framing offset, ie. srefclk and lrefclk are externally connected. tributary numbering tributary numbering for t1 and e1 uses the spe number, followed by the tributary number within that spe and are numbered sequentially. table 21 and table 22 show the t1 and e1 column numbering and relates the tributary number to the spe column numbers and overall sbi column structure. numbering for ds3 or e3 follows the same naming convention even though there is only one ds3 or e3 per spe. tvt1.5s and tvt2s follow the same numbering conventions as t1 and e1 tributaries respectively. sbi columns 16-18 are unused for t1, e1, tvt1.5 and tvt2 tributaries. table 21 - t1/tvt1.5 tributary column numbering t1# spe1 column spe2 column spe3 column sbi column 1,1 7,35,63 19,103,187 2,1 7,35,63 20,104,188 3,1 7,35,63 21,105,189 1,2 8,36,64 22,106,190
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 177 2,2 8,36,64 23,107,191 ??? 1,28 34,62,90 100,184,268 2,28 34,62,90 101,185,269 3,28 34,62,90 102,186,270 table 22 - e1/tvt2 tributary column numbering e1# spe1 column spe2 column spe3 column sbi column 1,1 7,28,49,70 19,82,145,208 2,1 7,28,49,70 20,83,146,209 3,1 7,28,49,70 21,84,147,210 1,2 8,29,50,71 22,85,148,211 2,2 8,29,50,71 23,86,149,212 ??? 1,21 27,48,69,90 79,142,205,268 2,21 27,48,69,90 80,143,206,269 3,21 27,48,69,90 81,144,207,270 sbi timing master modes the temap-84 supports both synchronous and asynchronous sbi timing modes. synchronous modes apply only to t1 and e1 tributaries and are used with ingress elastic stores to rate adapt the receive tributaries to the fixed sbi data rate. asynchronous modes allow t1, e1, ds3 and transparent tributaries to float within the sbi structure to accommodate differences in timing. in synchronous sbi mode, the t1 ds0s and e1 timeslots are in a fixed format and do not move relative to the sbi structure. the sbi frame pulse, sac1fp or sdc1fp, in synchronous mode can be enabled to indicate cas signaling multi- frame alignment by pulsing once every 12 th 2khz frame pulse period. srefclk sets the ingress rate from the receive elastic store. in asynchronous modes, timing is communicated across the scaleable bandwidth interconnect by floating data structures within the sbi. payload indicator signals in the sbi control the position of the floating data structure and therefore the timing. when sources are running faster than the sbi the floating payload structure is advanced by an octet by passing an extra octet in the v3 octet locations (h3 octet for ds3 and e3 mappings). when the source is slower than the sbi the floating payload is retarded by leaving the octet after the v3 or h3 octet unused. both these rate adjustments are indicated by the sbi control signals.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 178 transparent vts can float in the sbi structure in two ways. the first method uses valid v1 and v2 pointers to indicate positive and negative pointer justifications. the second methods uses the sbi signals sdv5, sav5, sdpl and sapl to indicate rate adjustments. in the drop bus, the temap-84 will always provide both valid pointers with valid sdv5 and sdpl signals. on the sbi add bus, the temap-84 needs to be configured on a per tributary basis for either transparent vt mode. transparent vt operation is configured on a per tributary basis via the etvt and etvtptrdis bits in the ttmp tributary control registers. on the drop bus the temap-84 is timing master as determined by the arrival rate of data over the sbi. on the add bus the temap-84 can be either the timing master or the timing slave. when the temap-84 is the timing slave it receives its transmit timing information from the arrival rate of data across the sbi add bus. when the temap-84 is the timing master it signals devices on the sbi add bus to speed up or slow down with the justification request signal, sajust_req. the temap-84 as timing master indicates a speedup request to a link layer sbi device by asserting the justification request signal high during the v3 or h3 octet. when this is detected by the link layer it will speed up the channel by inserting extra data in the next v3 or h3 octet. the temap-84 indicates a slow down request to the link layer by asserting the justification request signal high during the octet after the v3 or h3 octet. when detected by the link layer it will retard the channel by leaving the octet following the next v3 or h3 octet unused. both advance and retard rate adjustments take place in the frame or multi-frame following the justification request. arbitrary bandwidth support data streams of an arbitrary bit rate up to the capacitry of an spe may be transported across the spes to and from the flexible bandwidth ports. when one (or more) of the sbi is programmed to support this, the sapl and sdpl signals may be asserted and deasserted at arbitrary times to allow precise control of the payload bit rate. on the drop bus, data received on the fbwdat[3:1] signals are collected into complete bytes and are presented on sddata[7:0] with sdpl asserted high. no flow control is implemented on the drop bus. on the add bus, the efwbdreq[3:1] signals request data at a specific rate. the data is read from a shallow fifo. to keep the fifo half full, the sajust_req output is asserted to fetch data across the add bus. in turn, the data source responds with data and the sapl signal asserted an equal or less number of cycles than sajust_req is asserted. significant latency is
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 179 tolerated. note that the some applications require an exact one-to-one correspondence between sajust_req and data bytes. sbi link rate information the temap-84 sbi bus provides a method for carrying link rate information between devices. two methods are specified, one for t1 and e1 channels and the second for ds3 and e3 channels. for t1 and e1, the link rate information is always generated on the drop bus and always ignored on the add bus. for ds3 and e3, only the clkrate field of the link rate byte is valid on the drop bus and the use is optional on the add bus as specified by the clk_mode[1:0] bits of the exsbi tributary control indirect access data register. link rate information is not available for tvts. these methods use the reference 19.44 mhz sbi clock and the sac1fp frame synchronization signal to measure channel clock ticks and clock phase for transport across the bus. the t1 and e1 method allows for a count of the number of t1 or e1 rising clock edges between 2 khz sdc1fp frame pulses. this count is encoded in clkrate[1:0] to indicate that the nominal number of clocks, one more than nominal or one less than nominal should be generated during the sdc1fp period. this method also counts the number of 19.44 mhz clock rising edges after sampling sdc1fp high to the next rising edge of the t1 or e1 clock, giving the ability to control the phase of the generated clock. the link rate information passed across the sbi bus via the v4 octet and is shown in table 23. table 24 shows the encoding of the clock count, clkrate[1:0], passed in the link rate octet. note that while the temap-84 generates valid link rate information on the sbi drop bus, it ignores the v4 byte on the add bus.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 180 table 23 - sbi t1/e1 link rate information sdc1fp ??? srefclk ??? t1/e1 clk ??? clock count phase link rate octet bit # 7 6 5:4 3:0 t1/e1 format alm 0 clkrate[1:0] phase[3:0] table 24 - sbi t1/e1 clock rate encoding clkrate[1:0] t1 clocks / 2khz e1 clocks / 2 khz ?00? ? nominal 772 1024 ?01? ? fast 773 1025 ?1x? ? slow 771 1023 the method for transferring ds3 link rate information across the sbi passes the encoded count of ds3 clocks between 2khz sac1fp/sdc1fp pulses in the same method used for t1/e1 tributaries, but does not pass any phase information. the other difference from t1/e1 link rate is that clkrate[1:0] indicates whether the nominal number of clocks are generated or if four fewer or four extra clocks are generated during the sac1fp/sdc1fp period. the format of the ds3 link rate octet is shown in table 25. this is passed across the sbi via the linkrate octet which follows the h3 octet in the column, see table 31. table 26 shows the encoding of the clock count, clkrate[1:0], passed in the link rate octet.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 181 table 25 - ds3 link rate information link rate octet bit # 7 6 5:4 3:0 ds3 format alm 0 clkrate[1:0] unused table 26 - ds3 clock rate encoding clkrate[1:0] ds3 clocks / 2khz ?00? ? nominal 22368 ?01? ? fast 22372 ?1x? ? slow 22364 sbi alarms the temap-84 transfers alarm conditions across the sbi for t1, e1 and ds3 tributaries but not valid for transparent vts. table 23 and table 25 show the alarm indication bit, alm, as bit 7 of the link rate octet. devices connecting to the temap-84 which do not support alarm indications must set this bit to 0 on the sbi add bus. the presence of an alarm condition is indicated by the alm bit set high in the link rate octet. for t1 and e1 tributaries, either an out-of-frame condition or red alarm (persistent out-of-frame) may set the alm as determined by the ireden and ioofen per-tributary configuration bits. the absence of an alarm condition is indicated by the alm bit set low in the link rate octet. in the egress direction the temap-84 can be configured to use the alarm bit to force ais on a per link basis by the ealmen or egralmen register bits. t1 tributary mapping table 27 shows the format for mapping 84 t1s within the spe octets. the ds0s and framing bits within each t1 are easily located within this mapping for sonet/sdh byte synchronously mapped t1 applications. unframed t1s use the exact same format for mapping 84 t1s into the sbi except that the t1 tributaries need not align with the frame bit and ds0 locations. the v1,v2 and v4 octets are not used to carry t1 data and are either reserved or used for control across the interface. when enabled, the v4 octet is the link rate octet of table 23. it carries alarm and clock phase information across the sbi bus. the v1 and v2 octets are unused and should be ignored by devices listening to
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 182 the sbi bus. the v5 and r octets do not carry any information and are fixed to a zero value. the v3 octet carries a t1 data octet but only during rate adjustments as indicated by the v5 indicator signals, dv5 and av5, and payload signals, sdpl and sapl. the ppssssfr octets carry channel associated signaling (cas) bits and the t1 framing overhead. the ds0 octets are the 24 ds0 channels making up the t1 link. the v1,v2,v3 and v4 octets are fixed to the locations shown. all the other octets, shown shaded for t1#1,1, float within the allocated columns maintaining the same order and moving a maximum of one octet per 2khz multi-frame. the position of the floating t1 is identified via the v5 indicator signals, sdv5 and sav5, which locate the v5 octet. when the t1 tributary rate is faster than the sbi nominal t1 tributary rate, the t1 tributary is shifted ahead by one octet which is compensated by sending an extra octet in the v3 location. when the t1 tributary rate is slower than the nominal sbi tributary rate the t1 tributary is shifted by one octet which is compensated by inserting a stuff octet in the octet immediately following the v3 octet and delaying the octet that was originally in that position. table 27 - t1 framing format col # t1#1,1 t1#2,1-3,28 t1#1,1 t1#2,1-3,28 t1#1,1 t1#2,1-3,28 row # 1-18 19 20-102 103 104-186 187 188-270 1 unused v1 v1 v5 - ppssssfr - 2 unused ds0#1 - ds0#2 - ds0#3 - 3 unused ds0#4 - ds0#5 - ds0#6 - 4 unused ds0#7 - ds0#8 - ds0#9 - 5 unused ds0#10 - ds0#11 - ds0#12 - 6 unused ds0#13 - ds0#14 - ds0#15 - 7 unused ds0#16 - ds0#17 - ds0#18 - 8 unused ds0#19 - ds0#20 - ds0#21 - 9 unused ds0#22 - ds0#23 - ds0#24 - 1 unused v2 v2 r - ppssssfr - 2 unused ds0#1 - ds0#2 - ds0#3 - 3 unused ds0#4 - ds0#5 - ds0#6 - 4 unused ds0#7 - ds0#8 - ds0#9 - 5 unused ds0#10 - ds0#11 - ds0#12 - 6 unused ds0#13 - ds0#14 - ds0#15 - 7 unused ds0#16 - ds0#17 - ds0#18 - 8 unused ds0#19 - ds0#20 - ds0#21 - 9 unused ds0#22 - ds0#23 - ds0#24 - 1 unused v3 v3 r - ppssssfr - 2 unused ds0#1 - ds0#2 - ds0#3 - 3 unused ds0#4 - ds0#5 - ds0#6 -
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 183 4 unused ds0#7 - ds0#8 - ds0#9 - 5 unused ds0#10 - ds0#11 - ds0#12 - 6 unused ds0#13 - ds0#14 - ds0#15 - 7 unused ds0#16 - ds0#17 - ds0#18 - 8 unused ds0#19 - ds0#20 - ds0#21 - 9 unused ds0#22 - ds0#23 - ds0#24 - 1 unused v4 v4 r - ppssssfr - 2 unused ds0#1 - ds0#2 - ds0#3 - 3 unused ds0#4 - ds0#5 - ds0#6 - 4 unused ds0#7 - ds0#8 - ds0#9 - 5 unused ds0#10 - ds0#11 - ds0#12 - 6 unused ds0#13 - ds0#14 - ds0#15 - 7 unused ds0#16 - ds0#17 - ds0#18 - 8 unused ds0#19 - ds0#20 - ds0#21 - 9 unused ds0#22 - ds0#23 - ds0#24 - the p 1 p 0 s 1 s 2 s 3 s 4 fr octet carries t1 framing in the f bit and channel associated signaling in the p 1 p 0 and s 1 s 2 s 3 s 4 bits. channel associated signaling is optional and only available for sonet/sdh byte synchronously mapped tributaries. the r bit is reserved and is set to 0. the p 1 p 0 bits are used to indicate the phase of the channel associated signaling and the s 1 s 2 s 3 s 4 bits are the channel associated signaling bits for the 24 ds0 channels in the t1. table 28 shows the channel associated signaling bit mapping and how the phase bits locate the sixteen state cas mapping for super frame and extended superframe formats. when using four state cas then the signaling bits are a1-a24, b1-b24, a1-a24, b1-b24 in place of are a1-a24, b1-b24, c1-c24, d1-d24. when using 2 state cas there are only a1-a24 signaling bits. for unframed tributaries, the r, p and s bits are unused. when the synch_trib bit is set for a tributary, the ds0 alignment is precisely as presented in table 27, and the p 1 p 0 and s 1 s 2 s 3 s 4 bits in the first row of table 28 are aligned to the multiframe indicated by the sdc1fp signal, be it an input or output. the f-bit positions in table 28 have an arbitrary alignment relative to the p 1 p 0 bits that will change with each controlled frame slip; that illustrated is only an example. table 28 - t1 channel associated signaling bits sf esf s 1 s 2 s 3 s 4 ffp 1 p 0 a1 a2 a3 a4 f1 m1 00 a5 a6 a7 a8 s1 c1 00 a9 a10 a11 a12 f2 m2 00 a13 a14 a15 a16 s2 f1 00
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 184 a17 a18 a19 a20 f3 m3 00 a21 a22 a23 a24 s3 c2 00 b1 b2 b3 b4 f4 m4 01 b5 b6 b7 b8 s4 f2 01 b9 b10 b11 b12 f5 m5 01 b13 b14 b15 b16 s5 c3 01 b17 b18 b19 b20 f6 m6 01 b21 b22 b23 b24 s6 f3 01 c1 c2 c3 c4 f1 m7 10 c5 c6 c7 c8 s1 c4 10 c9 c10 c11 c12 f2 m8 10 c13 c14 c15 c16 s2 f4 10 c17 c18 c19 c20 f3 m9 10 c21 c22 c23 c24 s3 c5 10 d1 d2 d3 d4 f4 m10 11 d5 d6 d7 d8 s4 f5 11 d9 d10 d11 d12 f5 m11 11 d13 d14 d15 d16 s5 c6 11 d17 d18 d19 d20 f6 m12 11 d21 d22 d23 d24 s6 f6 11 t1 tributary asynchronous timing is compensated via the v3 octet. t1 tributary link rate adjustments are optionally passed across the sbi via the v4. t1 tributary alarm conditions are optionally passed across the sbi bus via the link rate octet in the v4 location. in synchronous mode, the t1 tributary mapping is fixed to that shown in table 27 and rate justifications are not possible using the v3 octet. the clock rate information within the link rate octet in the v4 location is not used in synchronous mode. e1 tributary mapping table 29 shows the format for mapping 63 e1s within the spe octets. the timeslots and framing bits within each e1 are easily located within this mapping for sonet/sdh byte synchronously mapped e1 applications. unframed e1s use the exact same format for mapping 63 e1s into the sbi except that the e1 tributaries need not align with the timeslot locations associated with channelized e1 applications. the v1,v2 and v4 octets are not used to carry e1 data and are either reserved or used for control information across the interface. when enabled, the v4 octet carries clock phase information across the sbi. the v1 and v2 octets are unused and should be ignored by devices listening to the sbi bus. the v5 and r octets do not carry any information and are fixed to a zero value. the v3 octet carries an e1 data octet but only during rate adjustments as
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 185 indicated by the v5 indicator signals, sdv5 and sav5, and payload signals, sdpl and sapl. the pp octets carry channel associated signaling phase information and e1 multiframe alignment. ts#0 through ts#31 make up the e1 channel. the v1,v2,v3 and v4 octets are fixed to the locations shown. all the other octets, shown shaded for e1#1,1, float within the allocated columns maintaining the same order and moving a maximum of one octet per 2khz multi-frame. the position of the floating e1 is identified via the v5 indicator signals, sdv5 and sav5, which locate the v5 octet. when the e1 tributary rate is faster than the e1 tributary nominal rate, the e1 tributary is shifted ahead by one octet which is compensated by sending an extra octet in the v3 location. when the e1 tributary rate is slower than the nominal rate the e1 tributary is shifted by one octet which is compensated by inserting a stuff octet in the octet immediately following the v3 octet and delaying the octet that was originally in that position. when the synch_trib bit is set for a tributary, the timeslot alignment is precisely as presented in table 29. table 29 - e1 framing format col # e1#1,1 #2,1-3,21 e1#1,1 #2,1-3,21 e1#1,1 #2,1-3,21 e1#1,1 #2,1-3,21 row # 1-18 19 20-81 82 83-144 145 146-207 208 209-270 1 unused v1 v1 v5 - pp - ts#0 - 2 unused ts#1 - ts#2 - ts#3 - ts#4 - 3 unused ts#5 - ts#6 - ts#7 - ts#8 - 4 unused ts#9 - ts#10 - ts#11 - ts#12 - 5 unused ts#13 - ts#14 - ts#15 - ts#16 - 6 unused ts#17 - ts#18 - ts#19 - ts#20 - 7 unused ts#21 - ts#22 - ts#23 - ts#24 - 8 unused ts#25 - ts#26 - ts#27 - ts#28 - 9 unused ts#29 - ts#30 - ts#31 - r - 1 unused v2 v2 r - pp - ts#0 - 2 unused ts#1 - ts#2 - ts#3 - ts#4 - 3 unused ts#5 - ts#6 - ts#7 - ts#8 - 4 unused ts#9 - ts#10 - ts#11 - ts#12 - 5 unused ts#13 - ts#14 - ts#15 - ts#16 - 6 unused ts#17 - ts#18 - ts#19 - ts#20 - 7 unused ts#21 - ts#22 - ts#23 - ts#24 - 8 unused ts#25 - ts#26 - ts#27 - ts#28 - 9 unused ts#29 - ts#30 - ts#31 - r - 1 unused v3 v3 r - pp - ts#0 - 2 unused ts#1 - ts#2 - ts#3 - ts#4 - 3 unused ts#5 - ts#6 - ts#7 - ts#8 -
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 186 4 unused ts#9 - ts#10 - ts#11 - ts#12 - 5 unused ts#13 - ts#14 - ts#15 - ts#16 - 6 unused ts#17 - ts#18 - ts#19 - ts#20 - 7 unused ts#21 - ts#22 - ts#23 - ts#24 - 8 unused ts#25 - ts#26 - ts#27 - ts#28 - 9 unused ts#29 - ts#30 - ts#31 - r - 1 unused v4 v4 r - pp - ts#0 - 2 unused ts#1 - ts#2 - ts#3 - ts#4 - 3 unused ts#5 - ts#6 - ts#7 - ts#8 - 4 unused ts#9 - ts#10 - ts#11 - ts#12 - 5 unused ts#13 - ts#14 - ts#15 - ts#16 - 6 unused ts#17 - ts#18 - ts#19 - ts#20 - 7 unused ts#21 - ts#22 - ts#23 - ts#24 - 8 unused ts#25 - ts#26 - ts#27 - ts#28 - 9 unused ts#29 - ts#30 - ts#31 - r - when using channel associated signaling (cas) ts#16 carries the abcd signaling bits and the timeslots 17 through 31 are renumbered 16 through 30. the pp octet is 0h for all frames except for the frame which carries the cas for timeslots 15/30 at which time the pp octet is c0h. the first octet of the cas multi-frame, rrrrrrrr, is reserved and should be ignored by the receiver when cas signaling is enabled. table 30 shows the format of timeslot 16 when carrying channel associated signaling. table 30 - e1 channel associated signaling bits ts#16[0:3] ts#16[4:7] pp rrrr rrrr 00 abcd1 abcd16 00 abcd2 abcd17 00 abcd3 abcd18 00 abcd4 abcd19 00 abcd5 abcd20 00 abcd6 abcd21 00 abcd7 abcd22 00 abcd8 abcd23 00 abcd9 abcd24 00 abcd10 abcd25 00 abcd11 abcd26 00 abcd12 abcd27 00 abcd13 abcd28 00 abcd14 abcd29 00 abcd15 abcd30 c0
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 187 e1 tributary asynchronous timing is compensated via the v3 octet. e1 tributary link rate adjustments are optionally passed across the sbi via the v4 octet. e1 tributary alarm conditions are optionally passed across the sbi bus via the link rate octet in the v4 location. in synchronous mode the e1 tributary mapping is fixed to that shown in table 29 and rate justifications are not possible using the v3 octet. the clock rate information within the link rate octet in the v4 location is not used in synchronous mode. ds3 tributary mapping table 31 shows a ds3 tributary mapped within the first synchronous payload envelope spe1. the v5 indicator pulse identifies the v5 octet. the ds3 framing format does not follow an 8khz frame period so the floating ds3 multi-frame located by the v5 indicator, shown in heavy border grey region in table 31, will jump around relative to the h1 frame on every pass. in fact the v5 indicator will often be asserted twice per h1 frame, as is shown by the second v5 octet in table 31. the v5 indicator and payload signals indicate negative and positive rate adjustments which are carried out by either putting a data byte in the h3 octet or leaving empty the octet after the h3 octet. table 31 - ds3 framing format spe col # ds3 1 ds3 2-56 ds3 57 ds3 58-84 ds3 col 85 row sbi col# 1,4,7,10 13 16 ??? ??? ??? ??? 184 ??? ??? ??? ??? 268 1 unused h1 v5 ds3 ds3 ds3 ds3 2 unused h2 ds3 ds3 ds3 ds3 ds3 3 unused h3 ds3 ds3 ds3 ds3 ds3 4 unused linkrate ds3 ds3 ds3 ds3 ds3 5 unused unused ds3 ds3 ds3 ds3 ds3 6 unused unused ds3 ds3 ds3 ds3 ds3 7 unused unused ds3 ds3 ds3 ds3 ds3 8 unused unused ds3 ds3 v5 ds3 ds3 9 unused unused ds3 ds3 ds3 ds3 ds3 because the ds3 tributary rate is less than the rate of the grey region, padding octets are interleaved with the ds3 tributary to make up the difference in rate. interleaved with every ds3 multi-frame are 35 stuff octets, one of which is the v5 octet. these 35 stuff octets are spread evenly across seven ds3 subframes. each ds3 subframe is eight blocks of 85 bits. the 85 bits making up a ds3 block are padded out to be 11 octets. table 32 shows the ds3 block 11 octet format where r indicates a stuff bit, f indicates a ds3 framing bit and i indicates
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 188 ds3 information bits. table 33 shows the ds3 multi-frame format that is packed into the grey region of table 31. in this table v5 indicates the v5 octet which is also a stuff octet, r indicates a stuff octet and b indicates the 11 octet ds3 block. each row in table 33 is a ds3 multi-frame. the ds3 multi-frame stuffing format is identical for 5 multi-frames and then an extra stuff octet after the v5 octet is added every sixth frame. table 32 - ds3 block format octet # 1 234567891011 data rrrfiiii 8*i 8*i 8*i 8*i 8*i 8*i 8*i 8*i 8*i 8*i table 33 - ds3 multi-frame stuffing format v5 4*r 8*b 5*r 8*b 5*r 8*b 5*r 8*b 5*r 8*b 5*r 8*b 5*r 8*b v5 4*r 8*b 5*r 8*b 5*r 8*b 5*r 8*b 5*r 8*b 5*r 8*b 5*r 8*b v5 4*r 8*b 5*r 8*b 5*r 8*b 5*r 8*b 5*r 8*b 5*r 8*b 5*r 8*b v5 4*r 8*b 5*r 8*b 5*r 8*b 5*r 8*b 5*r 8*b 5*r 8*b 5*r 8*b v5 4*r 8*b 5*r 8*b 5*r 8*b 5*r 8*b 5*r 8*b 5*r 8*b 5*r 8*b v5 5*r 8*b 5*r 8*b 5*r 8*b 5*r 8*b 5*r 8*b 5*r 8*b 5*r 8*b ds3 asynchronous timing is compensated via the h3 octet. ds3 link rate adjustments are optionally passed across the sbi via the linkrate octet. ds3 alarm conditions are optionally passed across the sbi bus via the linkrate octet. e3 tributary mapping table 34 shows a e3 tributary mapped within the first synchronous payload envelope spe1. the v5 indicator pulse identifies the v5 octet. the e3 framing format does not follow an 8khz frame period so the floating frame located by the v5 indicator and shown in grey in table 34, will jump around relative to the h1 frame on every pass. in fact the v5 indicator will be asserted two or three times per h1 frame, as is shown by the second and third v5 octet in table 34. the v5 indicator and payload signals indicate negative and positive rate adjustments which are carried out by either putting a data byte in the h3 octet or leaving empty the octet after the h3 octet.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 189 table 34 - e3 framing format spe col # e3 1 e3 2-18 e3 19 e3 20-38 e3 39 e3 40-84 e3 85 row sbi col# 1,4,7,10 13 16 ??? ??? ??? ??? 70 ??? ??? ??? ??? 130 ??? ??? ??? ??? 268 1 unused h1 v5 e3 e3 e3 e3 e3 e3 2 unused h2 e3 e3 e3 e3 e3 e3 e3 3 unused h3 e3 e3 e3 e3 e3 e3 e3 4 unused linkrate e3 e3 v5 e3 e3 e3 e3 5 unused unused e3 e3 e3 e3 e3 e3 e3 6 unused unused e3 e3 e3 e3 e3 e3 e3 7 unused unused e3 e3 e3 e3 v5 e3 e3 8 unused unused e3 e3 e3 e3 e3 e3 e3 9 unused unused e3 e3 e3 e3 e3 e3 e3 because the e3 tributary rate is less than the rate of the gray region, padding octets are interleaved with the e3 tributary to make up the difference in rate. interleaved with every e3 frame is an alternating pattern of 81 and 82 stuff octets, one of which is the v5 octet. these 81 or 82 stuff octets are spread evenly across the e3 frame. each e3 subframe is 48 octet which is further broken into 4 equal blocks of 12 octets each. table 35 shows the alternating e3 frame stuffing format that is packed into the gray region of table 34. note that there are 6 stuff octets after the v5 octet in one frame and 5 stuff octets after the v5 octet in the next frame. in this table v5 indicates the v5 octet which is also a stuff octet, r indicates a stuff octet, d indicates an e3 data octet, fas indicates the first byte of the 10 bit e3 frame alignment signal.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 190 table 35 - e3 frame stuffing format v5 6*r fas 11*d 5*r 12*d 5*r 12*d 5*r 12*d 5*r fas 11*d 5*r 12*d 5*r 12*d 5*r 12*d 5*r fas 11*d 5*r 12*d 5*r 12*d 5*r 12*d 5*r fas 11*d 5*r 12*d 5*r 12*d 5*r 12*d v5 5*r fas 11*d 5*r 12*d 5*r 12*d 5*r 12*d 5*r fas 11*d 5*r 12*d 5*r 12*d 5*r 12*d 5*r fas 11*d 5*r 12*d 5*r 12*d 5*r 12*d 5*r fas 11*d 5*r 12*d 5*r 12*d 5*r 12*d e3 asynchronous timing is compensated via the h3 octet. e3 link rate adjustments are optionally passed across the sbi via the linkrate octet. e3 alarm conditions are optionally passed across the sbi bus via the linkrate octet. flexible bandwidth mapping when the opmode_spex[2:0] register bits for an spe are binary 100, the sbi is configured to transport an arbitrary bandwidth up to the capacity of an spe. in this mode the sdpl and sapl signals identify individual valid bytes. for each spe, every third byte in columns 16 through 270, inclusive, has the potential for presenting data. be aware that although columns 13 though 15 carry no payload, the byte positions for rows 1 through 4 are driven by the drop bus with sdpl unconditionally low. transparent vt1.5/tu11 mapping vt1.5 and tu11 virtual tributaries, tvt1.5s, are transported across the sbi bus in a similar manner to the t1 tributary mapping. table 36 shows the transparent structure where ?i? is used to indicate information bytes. there are two options when carrying virtual tributaries on the sbi bus, the primary difference being how the floating v5 payload is located. the first option is locked tvt mode which carries the entire vt1.5/tu11 virtual tributary indicated by the shaded region in table 36. locked is used to indicate that the location of the v1,v2 pointer is locked. the virtual tributary must have a valid v1,v2 pointer to locate the v5 payload. in this mode the v5 indicator and payload signals, sdv5, sav5, sdpl and sapl, may be generated but must be ignored by the receiving device. in locked mode timing is always sourced by the
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 191 transmitting side, therefore justification requests are not used and the sajust_req signal is ignored. other than the v1 and v2 octets which must carry valid pointers, all octets can carry data in any format. the location of the v1,v2,v3 and v4 octets is fixed to the locations shown in table 36. the second option is floating tvt mode which carries the payload comprised of the v5 and i octets within the shaded region of table 36. in this mode the v1,v2 pointers are still in a fixed location and may be valid but are ignored by the receiving device. the v5 indicator and payload signals, sdv5, sav5, sdpl and sapl, must be valid and are used to locate the floating payload. the justification request signal can be used to control the timing on the add bus. the location of the v1,v2,v3 and v4 octets is fixed to the locations shown in table 36. the temap-84 supports both tvt modes simultaneously in the sbi drop bus and is configurable on a per tributary basis in the sbi add bus. table 36 - transparent vt1.5/tu11 format col # vt1.5#1,1 #2,1-3,28 vt1.5#1,1 #2,1-3,28 vt1.5#1,1 #2,1-3,28 row # 1-18 19 20-102 103 104-186 187 188-270 1 unused v1 v1 v5 - i - 2 unused i - i - i - 3 unused i - i - i - 4 unused i - i - i - 5 unused i - i - i - 6 unused i - i - i - 7 unused i - i - i - 8 unused i - i - i - 9 unused i - i - i - 1 unused v2 v2 i - i - 2 unused i - i - i - 3 unused i - i - i - 4 unused i - i - i - 5 unused i - i - i - 6 unused i - i - i - 7 unused i - i - i - 8 unused i - i - i - 9 unused i - i - i - 1 unused v3 v3 i - i - 2 unused i - i - i - 3 unused i - i - i - 4 unused i - i - i -
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 192 5 unused i - i - i - 6 unused i - i - i - 7 unused i - i - i - 8 unused i - i - i - 9 unused i - i - i - 1 unused v4 v4 i - i - 2 unused i - i - i - 3 unused i - i - i - 4 unused i - i - i - 5 unused i - i - i - 6 unused i - i - i - 7 unused i - i - i - 8 unused i - i - i - 9 unused i - i - i - transparent vt2/tu12 mapping vt2 and tu12 virtual tributaries, tvt2s, are transported across the sbi bus in a similar manner to the e1 tributary mapping. the temap-84 supports both tvt modes simultaneously in the sbi drop bus and is configurable on a per tributary basis in the sbi add bus. table 37 shows the transparent structure where ?i? is used to indicate information bytes. there are two options when carrying virtual tributaries on the sbi bus, the primary difference being how the floating v5 payload is located. the first option is locked tvt mode which carries the entire vt2/tu12 virtual tributary indicated by the shaded region in table 37. the term locked is used to indicate that the location of the v1,v2 pointer is locked. the virtual tributary must have a valid v1,v2 pointer to locate the v5 payload. in this mode the v5 indicator and payload signals, sdv5, sav5, sdpl and sapl, are optionally generated but must be ignored by the receiving device. in locked mode timing is always sourced by the transmitting side, therefore justification requests are not used and the sajust_req signal is ignored. other than the v1 and v2 octets which are carrying valid pointers, all octets can carry data in any format. the location of the v1,v2,v3 and v4 octets is fixed to the locations shown in table 37. the second option is floating tvt mode which carries the payload comprised of the v5 and i octets within the shaded region of table 37. in this mode the v1,v2 pointers are still in a fixed location and may be valid but are ignored by the receiving device. the v5 indicator and payload signals, sdv5, sav5, sdpl and sapl, must be valid and are used to locate the floating payload. the justification
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 193 request signal can be used to control the timing on the add bus. the location of the v1,v2,v3 and v4 octets is fixed to the locations shown in table 37. the temap-84 supports both tvt modes simultaneously in the sbi drop bus and is configurable on a per tributary basis in the sbi add bus.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 194 table 37 - transparent vt2/tu12 format col # e1#1,1 #2,1-3,21 e1#1,1 #2,1-3,21 e1#1,1 #2,1-3,21 e1#1,1 #2,1-3,21 row # 1-18 19 20-81 82 83-144 145 146-207 208 209-270 1 unused v1 v1 v5 - i - i - 2 unused i - i - i - i - 3 unused i - i - i - i - 4 unused i - i - i - i - 5 unused i - i - i - i - 6 unused i - i - i - i - 7 unused i - i - i - i - 8 unused i - i - i - i - 9 unused i - i - i - i - 1 unused v2 v2 i - i - i - 2 unused i - i - i - i - 3 unused i - i - i - i - 4 unused i - i - i - i - 5 unused i - i - i - i - 6 unused i - i - i - i - 7 unused i - i - i - i - 8 unused i - i - i - i - 9 unused i - i - i - i - 1 unused v3 v3 i - i - i - 2 unused i - i - i - i - 3 unused i - i - i - i - 4 unused i - i - i - i - 5 unused i - i - i - i - 6 unused i - i - i - i - 7 unused i - i - i - i - 8 unused i - i - i - i - 9 unused i - i - i - i - 1 unused v4 v4 i - i - i - 2 unused i - i - i - i - 3 unused i - i - i - i - 4 unused i - i - i - i - 5 unused i - i - i - i - 6 unused i - i - i - i - 7 unused i - i - i - i -
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 195 col # e1#1,1 #2,1-3,21 e1#1,1 #2,1-3,21 e1#1,1 #2,1-3,21 e1#1,1 #2,1-3,21 row # 1-18 19 20-81 82 83-144 145 146-207 208 209-270 8 unused i - i - i - i - 9 unused i - i - i - i -
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 196 12.12 jtag support the temap-84 supports the ieee boundary scan specification as described in the ieee 1149.1 standards. the test access port (tap) consists of the five standard pins, trstb, tck, tms, tdi and tdo used to control the tap controller and the boundary scan registers. the trstb input is the active-low reset signal used to reset the tap controller. tck is the test clock used to sample data on input, tdi and to output data on output, tdo. the tms input is used to direct the tap controller through its states. the basic boundary scan architecture is shown below. figure 27 - boundary scan architecture boundary scan register control tdi tdo device identification register bypass register instruction register and decode trstb tms tck test access port controller mux dff select tri-state enable
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 197 the boundary scan architecture consists of a tap controller, an instruction register with instruction decode, a bypass register, a device identification register and a boundary scan register. the tap controller interprets the tms input and generates control signals to load the instruction and data registers. the instruction register with instruction decode block is used to select the test to be executed and/or the register to be accessed. the bypass register offers a single- bit delay from primary input, tdi to primary output, tdo. the device identification register contains the device identification code. the boundary scan register allows testing of board inter-connectivity. the boundary scan register consists of a shift register placed in series with device inputs and outputs. using the boundary scan register, all digital inputs can be sampled and shifted out on primary output, tdo. in addition, patterns can be shifted in on primary input, tdi, and forced onto all digital outputs. 12.12.1 tap controller the tap controller is a synchronous finite state machine clocked by the rising edge of primary input, tck. all state transitions are controlled using primary input, tms. the finite state machine is described below.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 198 figure 28 - tap controller finite state machine test-logic-reset run-test-idle select-dr-scan select-ir-scan capture-dr capture-ir shift-dr shift-ir exit1-dr exit1-ir pause-dr pause-ir exit2-dr exit2-ir update-dr update-ir trstb=0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 all transitions dependent on input tms 0 0 0 0 0 1
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 199 test-logic-reset the test logic reset state is used to disable the tap logic when the device is in normal mode operation. the state is entered asynchronously by asserting input, trstb. the state is entered synchronously regardless of the current tap controller state by forcing input, tms high for 5 tck clock cycles. while in this state, the instruction register is set to the idcode instruction. run-test-idle the run test/idle state is used to execute tests. capture-dr the capture data register state is used to load parallel data into the test data registers selected by the current instruction. if the selected register does not allow parallel loads or no loading is required by the current instruction, the test register maintains its value. loading occurs on the rising edge of tck. shift-dr the shift data register state is used to shift the selected test data registers by one stage. shifting is from msb to lsb and occurs on the rising edge of tck. update-dr the update data register state is used to load a test register's parallel output latch. in general, the output latches are used to control the device. for example, for the extest instruction, the boundary scan test register's parallel output latches are used to control the device's outputs. the parallel output latches are updated on the falling edge of tck. capture-ir the capture instruction register state is used to load the instruction register with a fixed instruction. the load occurs on the rising edge of tck. shift-ir the shift instruction register state is used to shift both the instruction register and the selected test data registers by one stage. shifting is from msb to lsb and occurs on the rising edge of tck.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 200 update-ir the update instruction register state is used to load a new instruction into the instruction register. the new instruction must be scanned in using the shift-ir state. the load occurs on the falling edge of tck. the pause-dr and pause-ir states are provided to allow shifting through the test data and/or instruction registers to be momentarily paused. boundary scan instructions the following is a description of the standard instructions. each instruction selects a serial test data register path between input, tdi and output, tdo. bypass the bypass instruction shifts data from input, tdi to output, tdo with one tck clock period delay. the instruction is used to bypass the device. extest the external test instruction allows testing of the interconnection to other devices. when the current instruction is the extest instruction, the boundary scan register is placed between input, tdi and output, tdo. primary device inputs can be sampled by loading the boundary scan register using the capture-dr state. the sampled values can then be viewed by shifting the boundary scan register using the shift-dr state. primary device outputs can be controlled by loading patterns shifted in through input tdi into the boundary scan register using the update-dr state. sample the sample instruction samples all the device inputs and outputs. for this instruction, the boundary scan register is placed between tdi and tdo. primary device inputs and outputs can be sampled by loading the boundary scan register using the capture-dr state. the sampled values can then be viewed by shifting the boundary scan register using the shift-dr state. idcode the identification instruction is used to connect the identification register between tdi and tdo. the device's identification code can then be shifted out using the shift-dr state.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 201 stctest the single transport chain instruction is used to test out the tap controller and the boundary scan register during production test. when this instruction is the current instruction, the boundary scan register is connected between tdi and tdo. during the capture-dr state, the device identification code is loaded into the boundary scan register. the code can then be shifted out of the output, tdo, using the shift-dr state. boundary scan cells in the following diagrams, clock-dr is equal to tck when the current controller state is shift-dr or capture-dr, and unchanging otherwise. the multiplexer in the center of the diagram selects one of four inputs, depending on the status of select lines g1 and g2. the id code bit is as listed in the boundary scan register table in the jtag test port section 11.2. figure 29 - input observation cell (in_cell) input pad d c clock-dr scan chain out input to internal logic shift-dr scan chain in 1 2 mux 1 2 1 2 1 2 i.d. code bit idcode g1 g2
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 202 figure 30 - output cell (out_cell) extest d c d c g1 g2 12 mux g1 1 1 mux output or enable from system logic scan chain in scan chain out output or enable shift-dr clock-dr update-dr 12 12 12 idoode i.d. code bit figure 31 - bidirectional cell (io_cell) d c d c g1 1 1 mux output from internal logic scan chain in scan chain out extest output to pin shift-dr clock-dr update-dr input from pin input to internal logic g1 1 2 mux 1 2 1 2 1 2 g2 idcode i.d. code bit
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 203 figure 32 - layout of output enable and bidirectional cells output enable from internal logic (0 = drive) input to internal logic output from internal logic scan chain in scan chain out i/o pad out_cell io_cell
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 204 13 functional timing 13.1 ds3 line side interface timing all functional timing diagrams assume that polarity control is not being applied to input and output data and clock lines (i.e. polarity control bits in the temap-84 registers are set to their default states). figure 33 - receive bipolar ds3 stream rpos[x] rneg[x] 3 consec 0s lcv rclk[x] the receive bipolar ds3 stream diagram (figure 33) shows the operation of the temap-84 while processing a b3zs encoded ds3 stream on inputs rpos and rneg. it is assumed that the first bipolar violation (on rneg) illustrated corresponds to a valid b3zs signature. a line code violation is declared upon detection of three consecutive zeros in the incoming stream, or upon detection of a bipolar violation which is not part of a valid b3zs signature. figure 34 - receive unipolar ds3 stream rclk[x] rdati[x] x1 bit rlcv[x] x2 bit info 84 c bit info 1 info 2 info 3 info 4 info 5 or p or m bit or f bit info 84 info 1 lcv indication the receive unipolar ds3 stream diagram (figure 34) shows the complete ds3 receive signal on the rdat input. line code violation indications, detected by an upstream b3zs decoder, are indicated on input rlcv. rlcv is sampled each bit period. the pmon line code violation event counter is incremented each time a logic 1 is sampled on rlcv.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 205 figure 35 - receive bipolar e3 stream rclk[x] rpos[x] rneg[x] 4 consec 0s lcv x 0 0 v hdb3 signature pattern 0 0 0 v b v 0 0 the receive bipolar e3 stream diagram (figure 35) shows the operation of the temap-84 while processing an hdb3-encoded e3 stream on inputs rpos[x] and rneg[x]. it is assumed that the first bipolar violation (on rneg[x]) illustrated corresponds to a valid hdb3 signature. a line code violation is declared upon detection of four consecutive zeros in the incoming stream, or upon detection of a bipolar violation which is not part of a valid hdb3 signature. figure 36 - receive unipolar e3 stream rclk[x] rdati[x] fa1 1 rlcv[x] info x+1 info n info n+1 info n+2 info n+3 info n+4 info n+5 info n+6 info x fa1 2 lcv indication the receive unipolar e3 stream diagram (figure 36) shows the unipolar e3 receive signal on the rdati[x] input. line code violation indications, detected by an upstream hdb3 decoder, are indicated on input rlcv. rlcv is sampled each bit period. the pmon line code violation event counter is incremented each time a logic 1 is sampled on rlcv.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 206 figure 37 - transmit bipolar ds3 stream tclk[x] tpos[x] tneg[x] ticlk[x] 1 1 0 0 1 0 0 the transmit bipolar ds3 stream diagram illustrates the generation of a bipolar ds3 stream. the b3zs encoded ds3 stream is present on tpos and tneg. these outputs, along with the transmit clock, tclk, can be directly connected to a ds3 line interface unit. note that tclk is a flow through version of ticlk; a variable propagation delay exists between these two signals. figure 38 - transmit unipolar ds3 stream tclk[x] tdato[x] nib 1 bit 4 tmfp[x] ticlk[x] x1 x1 nib 1 bit 4 nib 1190 bit 1 nib 22 bit 4 x2 nib 21 bit 1 the transmit unipolar ds3 stream diagram (figure 38) illustrates the unipolar ds3 stream generation. the tmfp output marks the m-frame boundary, x1 bit, in the transmit stream. note that tclk is a flow through version of ticlk; a variable propagation delay exists between these two signals.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 207 figure 39 - transmit bipolar e3 stream tclk[x] tpos[x] tneg[x] x 0 0 v hdb3 signature pattern 0 0 0 v b v 0 0 ticlk[x] the transmit bipolar e3 stream diagram (figure 39) illustrates the generation of a bipolar e3 stream. the hdb3 encoded e3 stream is present on tpos and tneg. these outputs, along with the transmit clock, tclk, can be directly connected to a e3 line interface unit. note that tclk is a flow through version of ticlk; a variable propagation delay exists between these two signals. figure 40 - transmit unipolar e3 stream tclk[x] tdato[x] info x info x+1 tmfp[x] bip[0] bip[1] bip[2] bip[3] bip[4] bip[5] ticlk[x] fa1 2 fa1 1 info x+465 fa1 3 the transmit unipolar e3 stream diagram (figure 40) illustrates the unipolar e3 stream generation. the tmfp output shown marks the g.832 frame boundary (the first bit of the fa1 frame alignment byte) in the transmit stream. note that tclk is a flow through version of ticlk; a variable propagation delay exists between these two signals.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 208 13.2 ds3 and e3 system side interface timing figure 41 - framer mode ds3 transmit input stream tdati[x] info 84 tfpi/tmfpi[x] info 84 info 83 info 82 x1 info 2 info 1 x2 info 1info 2info 3 info 84 info 82 info 83 f4 info 82 info 83 tfpo/tmfpo[x] ticlk[x] figure 42 - framer mode ds3 transmit input stream with tgapclk tgapclk[x] tdati[x] info 1 info 83 info 82 info 81 info 3 info 2 info 2 info 3 info 4 info 1 info 83 info 84 info 83 info 84 ticlk[x] info 1 the framer mode ds3 transmit input stream diagram (figure 41) shows the expected format of the inputs tdat and tfpi/tmfpi along with ticlk and the output tfpo/tmfpo when the opmode_spex[2:0] bits are set to ?ds3/e3 framer only mode? in the spe configuration registers. if the txmfpi bit in the ds3 and e3 master unchannelized interface options register is logic 0, then tfpi is valid, and the temap-84 will expect tfpi to pulse for every ds3 overhead bit with alignment to tdati. if the txmfpi register bit is logic 1, then tmfpi is valid, and the temap-84 will expect tmfpi to pulse once every ds3 m-frame with alignment to tdati. if the txmfpo bit in the ds3 and e3 master unchannelized interface options register is logic 0, then tfpo is valid, and the temap-84 will pulse tfpo once every 85 ticlk cycles, providing upstream equipment with a reference ds3 overhead pulse. if the txmfpo register bit is logic 1, then tmfpo is valid and the temap-84 will pulse tmfpo once every 4760 ticlk cycles, providing upstream equipment with a reference m-frame pulse. the alignment of tfpo or tmfpo is arbitrary. there is no set relationship between tfpo/tmfpo and tfpi/tmfpi. the tgapclk output is available in place of tfpo/tmfpo when the txgapen bit in the ds3 and e3 master unchannelized interface options register is set to logic 1, as in figure 42. tgapclk remains high during the overhead bit positions.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 209 figure 43 - framer mode ds3 receive output stream rdato[x] info 84 rfpo/rmfpo[x] info 84 info 83 info 82 x1 info 2 info 1 x2 info 1 info 2 info 3 info 84 info 82 info 83 f4 info 82 info 83 rovrhd[x] rsclk[x] figure 44 - framer mode ds3 receive output stream with rgapclk rgapclk[x] rdato[x] info 84 info 84 info 83 info 82 info 2 info 1 info 1 info 2 info 3 info 84 info 82 info 83 info 82 info 83 info 84 the ds3/e3 framer only mode receive output stream diagram (figure 43) shows the format of the outputs rdato, rfpo/rmfpo, rsclk rovrhd when the opmode_spex[2:0] bits are set to ?ds3/e3 framer only mode? in the spe configuration registers. figure 43 shows the data streams when the temap-84 is configured for the ds3 receive format. if the rxmfpo bit in the ds3 and e3 master unchannelized interface options register is logic 0, rfpo is valid and will pulse high for one rsclk cycle on first bit of each m-subframe with alignment to the rdato data stream. if the rxmfpo register bit is a logic 1 (as shown figure 43), rmfpo is valid and will pulse high on the x1 bit of the rdato data output stream. rovrhd will be high for every overhead bit position on the rdato data stream. figure 44 shows the output data stream with rgapclk in place of rsclk when the rxgapen bit in the ds3 and e3 master unchannelized interface options register set to logic 1. rgapclk remains high during the overhead bit positions. figure 45 - framer mode g.751 e3 transmit input stream tdati[x] bit 1536 0 tfpi/tmfpi[x] nat rai 11 1 10100 bit 1531 bit 1529 bit 1530 bit 1532 bit 1533 bit 1534 bit 1535 tfpo/tmfpo[x] 0 bit13 ticlk[x]
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 210 figure 46 - framer mode g.751 e3 transmit input stream with tgapclk tgapclk[x] tdati[x] bit 1536 bit 1531 bit 1529 bit 1530 bit 1532 bit 1533 bit 1534 bit 1535 bit14 ticlk[x] bit13 the framer mode g.751 e3 transmit input stream diagrams (figure 45 and figure 46) show the expected format of the inputs tdati, tfpi/tmfpi, and ticlk and the output tfpo/tmfpo (and tgapclk) when the temap-84 is configured for the e3 g.751 transmit format. tfpi or tmfpi pulses high for one ticlk cycle and is aligned to the first bit of the frame alignment signal in the g.751 e3 input data stream on tdati. tfpo or tmfpo will pulse high for one out of every 1536 ticlk cycles, providing upstream equipment with a reference frame pulse. the alignment of tfpo or tmfpo is arbitrary. there is no set relationship between tfpo/tmfpo and tfpi/tmfpi. the tgapclk output is available in place of tfpo/tmfpo when the txgapen bit in the ds3 and e3 master unchannelized interface options register is set to logic 1, as in figure 46. tgapclk remains high during the overhead bit positions. tdati is sampled on the falling edge of tgapclk. figure 47 - framer mode g.751 e3 receive output stream rdato[x] bit 1536 0 rfpo/rmfpo[x] nat rai 1 1 1 1 0 100 bit 1531 bit 1529 bit 1530 bit 1532 bit 1533 bit 1534 bit 1535 rovrhd[x] 0 bit13 rsclk[x] figure 48 - framer mode g.751 e3 receive output stream with rgapclk rgapclk[x] rdato[x] bit 1536 bit 1531 bit 1529 bit 1530 bit 1532 bit 1533 bit 1534 bit 1535 bit13 the framer mode g.751 e3 receive output stream diagrams (figure 47 and figure 48) show the format of the outputs rdato, rfpo/rmfpo, rsclk (and rgapclk), and rovrhd when the temap-84 is configured for the e3 g.751 receive format. rfpo or rmfpo pulses high for one rsclk cycle and is
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 211 aligned to the first bit of the framing alignment signal in the g.751 e3 output data stream on rdato. rovrhd will be high for every overhead bit position on the rdato data stream. if the pyld&just register bit in the e3 frmr maintenance options register is set to logic 0, the c jk and p k bits in the rdato stream will be marked as overhead bits. if the pyld&just register bit is set to logic 1, the c jk and p k bits in the rdato stream will be marked as payload. the rgapclk output is available in place of rsclk when the rxgapen bit in the ds3 and e3 master unchannelized interface options register is set to logic 1. rgapclk remains high during the overhead bit positions as shown in figure 48. figure 49 - framer mode g.832 e3 transmit input stream tdati[x] oct 530 8 tfpi/tmfpi[x] oct n 3 oct n 2 oct n 1 fa1 1 fa1 4 fa1 3 fa1 2 fa1 5 fa1 6 fa1 7 fa1 8 oct 530 3 oct 530 1 oct 530 2 oct 530 4 oct 530 5 oct 530 6 oct 530 7 tfpo/tmfpo[x] ticlk[x] figure 50 - framer mode g.832 e3 transmit input stream with tgapclk tgapclk[x] tdati[x] oct 530 8 oct n 3 oct n 2 oct n 1 oct 530 3 oct 530 1 oct 530 2 oct 530 4 oct 530 5 oct 530 6 oct 530 7 ticlk[x] the framer mode g.832 e3 transmit input stream diagrams (figure 49 and figure 50) show the expected format of the inputs tdati, tfpi/tmfpi, and ticlk and the output tfpo/tmfpo (and tgapclk) when the temap-84 is configured for the e3 g.832 transmit format. tfpi or tmfpi pulses high for one ticlk cycle and is aligned to the first bit of the fa1 byte in the g.832 e3 input data stream on tdati. tfpo or tmfpo will pulse high for one out of every 4296 ticlk cycles, providing upstream equipment with a reference frame pulse. the alignment of tfpo or tmfpo is arbitrary. there is no set relationship between tfpo/tmfpo and tfpi/tmfpi. the tgapclk output is available in place of tfpo/tmfpo when the txgapen bit in the ds3 and e3 master unchannelized interface options register is set to logic 1, as in figure 50. tgapclk remains high during the overhead bit positions. tdati is sampled on the falling edge of tgapclk.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 212 figure 51 - framer mode g.832 e3 receive output stream rdato[x] oct 530 8 rfpo/rmfpo[x] oct 1 2 oct 1 1 fa2 8 fa1 1 fa1 4 fa1 3 fa1 2 fa1 5 fa1 6 fa1 7 fa1 8 oct 530 3 oct 530 1 oct 530 2 oct 530 4 oct 530 5 oct 530 6 oct 530 7 rovrhd[x] rsclk[x] figure 52 - framer mode g.832 e3 receive output stream with rgapclk rgapclk[x] rdato[x] oct 530 8 oct 1 2 oct 1 1 oct 530 3 oct 530 1 oct 530 2 oct 530 4 oct 530 5 oct 530 6 oct 530 7 the framer mode g.832 e3 receive output stream diagrams (figure 51 and figure 52) show the format of the outputs rdato, rfpo/rmfpo, rsclk (and rgapclk), and rovrhd when the temap-84 is configured for the e3 g.832 receive format. rfpo or rmfpo pulses high for one rsclk cycle and is aligned to the first bit of the fa1 byte in the g.832 e3 output data stream on rdato. rovrhd will be high for every overhead bit position on the rdato data stream. the rgapclk output is available in place of rsclk when the rxgapen bit in ds3 and e3 master unchannelized interface options register is set to logic 1. rgapclk remains high during the overhead bit positions as shown in figure 52. 13.3 telecom drop bus interface timing figure 53 shows the function of the various telecom drop bus signals in au3 mode. data on lddata[7:0] is sampled on the rising edge of lrefclk. the bytes forming the three sts-1 synchronous payload envelopes are identified when the ldpl signal is high. in this diagram, a negative stuff event is shown occurring on sts-1 #2 and a positive stuff event on sts-1 #3. the ldc1j1v1 signal pulses high, while ldpl is set low, to mark the c1 byte of the first sts-1 in every frame of the sts-3 transport envelope. the ldc1j1v1 signal is high when the ldpl signal is high to mark every j1 byte of each of the three sts-1 spes. the bytes forming the various tributary synchronous payload envelopes are identified by the ldtpl when set high. the ldv5 signal pulses high to mark the v5 bytes of each tributary. ldtpl and ldv5 are invalid when ldpl is set low. the three sts-1 spes can each have different alignments to the sts-3
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 213 transport envelope and the alignment is changing for two of the sts-1 spes (sts-1 #2 and #3) due to the pointer justification events shown. figure 53 - telecom drop bus timing - sts-1 spes / au3 vcs ldpl lrefclk ldc1j1 ldv5 invalid invalid iv iv ldtpl invalid invalid iv iv sts-1 #1 spe j1 byte lddata[7:0] a 1 a 1 a 2 a 2 a 2 c1c1c1 a 1 h1 h1 h2 h2 h2 h3 h3 h1 negative stuff for sts-1 #2 spe which happens to carry a non-final h4 byte v5 byte as marked by otv5 positive stuff for sts-1 #3 spe j1 h4 v x v5 any v1 - v4 byte tu#1, sts-1 #1 last h4 byte in tributary multiframe h4 c2 g1 the ldv5 and ldtpl signals are optional when using the ingress vtpp within the temap-84 which will regenerate the ldv5 and ldtpl signals from ldc1j1v1, ldpl and the pointers within lddata[7:0]. in order to bypass the ingress vtpp, the data on the telecom drop bus must be locked such that all three sts-1 spes are aligned to the sts-3 transport envelope with the j1 bytes immediately following the c1 bytes. this is shown in figure 54.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 214 figure 54 - telecom drop bus timing - locked sts-1 spes / au3 vcs lrefclk ldc1j1 ldpl ldtpl ldv5 implicit location of sts-1 spe j1 bytes lddata[7:0] a 2c1c1c1 h1 h1 h2 h2 h2 h3 h3 h1 h3 no stuff events possible v1 byte vt #1, sts-1 #1 v5 byte vt #1, sts-1 #2 j1 j1 j1 v1 v1 v1 v1 v1 v1 v1 v1 byte vt #1, sts-1 #2 v1 byte vt #1, sts-1 #3 v5 v1 bytes vt #2 j2 j2 byte vt #1, sts-1 #1 figure 55 shows the function of the various telecom drop bus signals in au4 mode. data on lddata [7:0] is sampled on the rising edge of lrefclk. the bytes forming the vc4 virtual container are identified by the setting the ldpl signal high. the ldc1j1v1 signal pulses high, while ldpl is set low, to mark the single c1 byte in every frame of the au4 transport envelope. the ldc1j1v1 signal is set high again with ldpl high to mark the j1 byte of the vc4. the bytes forming the various tributary synchronous payload envelopes are identified by the ldtpl signal being set high. the ldv5 signal pulses high to mark the v5 bytes of each outgoing tributaries.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 215 figure 55 - telecom drop bus timing - au4 vc lrefclk ldpl ldc1j1 lddat a [7:0] a1 a2 a2 a2 c1 x x v5 byte tug3 #1 national bytes v5 j1 v1 v1 v1 v1 byte tu #1, tug2 #1, tug3 #1 np np np first npi byte tug3 #1 j1 byte vc4 z7 z7 byte tug3 #1 ldt pl invalid ldv5 invalid the ldv5 and ldtpl signals are optional when using the ingress vtpp within the temap-84 which will regenerate the ldv5 and ldtpl signals from ldc1j1v1, ldpl and the pointers within lddata[7:0]. in order to bypass the ingress vtpp, the position of the single j1 byte and the vc4 is implicitly defined by the c1 byte position. in the locked au4 mode, the vc4 is defined to be aligned to the au4 transport envelope such that the j1 byte occupies the first available payload byte after the c1 byte, and no pointer justifications are possible. 13.4 telecom add bus interface timing figure 56 shows the function of the telecom add bus signals in au3 mode. data on ladata[7:0] is updated on the rising edge of lrefclk. the lac1 input is sampled on the rising edge of lrefclk and aligns all devices on the add bus by marking the first c1 byte of the first sts-1 in every fourth sts-3 transport envelope. lac1 pulses every fourth sts-3 to indicate tributary multiframe alignment on the add bus. the bytes forming the three sts-1 synchronous payload envelopes are identified when the lapl signal is high. the lac1j1v1 signal pulses high, while lapl is set low, to mark the c1 byte of the first sts-1 in every frame of the sts-3 transport envelope. the lac1j1v1 signal is high when the lapl signal is high to mark every j1 byte of each of the three sts-1 spes. the three sts-1 spes have an alignment determined by the sonet/sdh transmit pointer configuration registers. a pointer of 522 decimal is illustrated in figure 56.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 216 the lac1 signal is updated on the rising edge of lrefclk. it is output during when the temap-84 is outputing valid tributary data onto the add bus. it is asserted high for all bytes making up a tributary and is asserted low during overhead bytes. figure 56 - telecom add bus timing - locked sts-1 spes / au3 vcs lrefclk lac1 lac1j1v1 lapl implicit location of sts-1 spe j1 bytes ladata[7:0] a 2c1 c1c1 h1 h1 h2 h2 h2 h3 h3 h1 h3 no stuff events possible v1 byte vt #1, sts-1 #1 v5 byte vt #1, sts-1 #2 j1 j1 j1 v1 v1 v1 v1 v1 v1 v1 v1 byte vt #1, sts-1 #2 v1 byte vt #1, sts-1 #3 v5 v1 bytes vt #2 j2 j2 byte vt #1, sts-1 #1 laoe figure 57 shows the function of the temap-84 telecom add bus when operating in au4 mode. in au4 mode, the position of the single j1 byte and the vc4 is implicitly defined by the lac1 byte position. the vc4 is defined to be aligned to the au4 transport envelope such that the j1 byte occupies the first available payload byte after the c1 byte. no pointer justification events take place on the add bus. lac1j1v1 pulses high to mark the first c1 byte, the j1 byte and the third byte after j1 of the first tributary in the au4 stream. lapl identifies the payload bytes on ladata[7:0].
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 217 figure 57 - telecom add bus timing - locked au4 vc case lrefcl k lac1 laoe lapl lac1j1v1 implicit location of vc4 j1 byte ladata[7:0] a 2c1 x x h4 j1 national bytes first r column of tug3 #1 v5 v1 v1 byte tu #1, tug2 #1, tug3 #1 last h4 byte in tributary multiframe v5 byte tu #1, tug2 #1, tug3 #1 fixed stuff columns rrrrrr r rrr rr z6 z6 byte tu #1, tug2 #1, tug3 #3 13.4.1 notes on 77.76 mhz telecom bus operation telecom bus operation at 77.76mhz is simply a byte interleaved multiplex of a 19.44 mbyte/s stream with idle cycles. the stm-1 of interest is identified by the lstm[1:0] bits of the master bus configuration register. on the drop bus, the three unused stm-1s are simply ignored, including parity. on the add bus, the unused stm-1s are high-impedance by default, but the bus may be configured to drive continuously. the following is of special note: 1. regardless of the state of the lstm[1:0] bits, the lac1 input pulse always identifies the first of the twelve c1 bytes. 2. the lac1j1v1 output is only valid if the lstm[1:0] bit are ?00?. the c1 indication will identify the first of the twelve c1 bytes. the j1 will be high during either the first j1 byte or the first three j1 bytes depending on whether au3 or au4 mode is programmed. the same is true of the v1 pulse. if more than one device is driving the bus, all devices must use the same transmit payload pointer.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 218 3. up to four devices may be directly connected to the same bus. current consumption is minimized if all devices are the same (ie. all temap-84s). all devices must receive the same lac1 signal. 4. the incldc1j1v1 register bit may only be set if the lstm[1:0] bit are ?00?. 5. the telecom bus becomes unconditionally high-impedance upon either a hardware or software reset. all necessary configuration and at least one lac1 pulse should precede the setting of the laddoe or laoe register bits. 13.5 sonet/sdh serial alarm port timing the timing relationships of the signals related to the remote serial alarm port are shown in figure 58. the remote serial alarm port clocks, radeastck and radwestck, are nominally 9.72 mhz clocks but can range from 1.344 mhz to 10 mhz. the remote serial alarm port frame pulses, radeastfp and radwestfp, mark the first bip-2 error bit (b1 in figure 58) of the first tributary (tu #1 of tug2 #1, tug3 #1) on radeast and radwest, respectively. the frame pulses must be set high to mark every first bip-2 error bit of the first tributary. tributaries on radeast and radwest are arranged in the order of transmission of an stm-1 stream as defined in the references. i.e., tu #1 of tug2 #1 in tug3 #1, tu#1 of tug2 #1 in tug3 #2, tu#1 of tug2 #1 in tug3 #3, tu#1 of tug2 #2 in tug3 #1, ... tu #1 of tug2 #7 in tug3 #3, tu #2 of tug2 #1 in tug3 #1, ... tu #2 of tug2 #7 in tug3 #3, tu #3 of tug2 #1 in tug3 #1, ... tu #4 of tug2 #7 in tug3 #3. timeslot assignment on radeast and radwest is unrelated to the configuration of the tug2. timeslots are always reserved for four tributaries in every tug2 even if it is configured for tributaries with higher bandwidth than tu11, such as tu12. at timeslots devoted to non-existent tributaries, for example, tributary 4 of a tug2 configured for tu12, radeast and radwest will be ignored. each tributary in the remote serial alarm port is allocated eight timeslots. the first two timeslots, labeled b1 and b2 in figure 58, reports the two possible bip-2 errors in the tributary payload frame. an alarm contributing to remote defect indications is reported in the third timeslot and is labeled d in figure 58. the timeslot labeled f report alarms contributing to remote failure indications. in extended rdi mode, the d and f bits are considered as two bit codepoint and will be reported on the rdi and rfi signals. out of extended rdi mode, the d and f bits are independent. the remaining four timeslots are unused and are ignored.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 219 figure 58 - remote serial alarm port timing radeastfp/ radwestfp x radeast/ radwest b1 b2 d f x x xx b1 b2 df xx xx b1 b2 df xx xx b1 b2 df x xx tu #1, tug2 #1, tug3 #1 tu #1, tug2 #1, tug3 #2 tu #1, t ug2 #1, tug3 #3 tu #1, tug2 #2, tug3 #1 radeastfp/ radwestfp ... tu #1, tug 2 #1 tug3 #1 tug3 #2 tug3 #3 tug3 #1 tug3 #2 tug3 #3 tug3 #1 tug3 #2 tu #1, tug2 #2 tug2 #3 tu #4, tug 2 #7 tug3 #2 tug3 #3 tug3 #1 tug3 #2 tug3 #3 x tug2 #6 x radeastck/ radwestck radeastck/ radwestck 13.6 sbi drop bus interface timing figure 59 - sbi drop bus t1/e1 functional timing c1 v3 v3 v3 ds0#4. v5 ds0#9. srefclk sc1fp sddata[7:0] sdpl sdv5 sddp ??? ??? ??? ??? ??? ??? figure 59 illustrates the operation of the sbi drop bus, using a negative justification on the second to last v3 octet as an example. the justification is indicated by asserting sdpl high during the v3 octet. the timing diagram also shows the location of one of the tributaries by asserting sdv5 high during the v5 octet.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 220 figure 60 - sbi drop bus ds3/e3 functional timing c1 h3 h3 h3 ds-3 #1 ds-3 #2 ds-3 #3 ds-3 #1 srefclk sc1fp sddata[7:0 ] sdpl sdv5 sddp ??? ??? ??? ??? ??? ??? figure 60 shows three ds-3 tributaries mapped onto the sbi bus. a negative justification is shown for ds-3 #2 during the h3 octet with sdpl asserted high. a positive justification is shown for ds-3#1 during the first ds-3#1 octet after h3 which has sdpl asserted low. e3 is transported by the same mechanism. 13.7 sbi add bus interface timing the sbi add bus functional timing for the transfer of tributaries whether t1/e1 or ds3 is the same as for the sbi drop bus. the only difference is that the sbi add bus has one additional signal: the sajust_req output. the sajust_req signal is used to by the temap-84 in sbi master timing mode to provide transmit timing to sbi link layer devices. figure 61 - sbi add bus justification request functional timing c1 h3 h3 h3 ds-3 #1 ds-3 #2 ds-3 #3 ds-3 #1 srefclk sc1fp sadata[7:0] sapl sav5 sadp sajust_req ??? ??? ??? ??? ??? ??? ???
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 221 figure 61 illustrates the operation of the sbi add bus, using positive and negative justification requests as an example. (the responses to the justification requests would take effect during the next multi-frame.) the negative justification request occurs on the ds-3#3 tributary when sajust_req is asserted high during the h3 octet. the positive justification occurs on the ds-3#2 tributary when sajust_req is asserted high during the first ds-3#2 octet after the h3 octet. 13.7.1 notes on 77.76 mhz sbi bus operation sbi bus operation at 77.76mhz is simply a byte interleaved multiplex of a 19.44 mbyte/s stream with idle cycles. the stm-1 of interest is identified by the lstm[1:0] bits of the master bus configuration register. on the add bus, the three unused stm-1s are simply ignored, including parity. on the drop bus, the unused stm-1s are high-impedance. the following is of special note: 1. regardless of the state of the sstm[1:0] bits, the sac1fp and sdc1fp pulses always identify the first byte of the frame. 2. up to four devices may be directly connected to the same bus. current consumption is minimized if all devices are the same (ie. all temap-84s). all devices must receive the same sac1fp and sdc1fp signals. 3. the telecom bus becomes unconditionally high-impedance upon either a hardware or software reset. all necessary configuration and at least one sdc1fp pulse should precede the setting of the gsoe register bit.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 222 14 absolute maximum ratings maximum rating are the worst case limits that the device can withstand without sustaining permanent damage. they are not indicative of normal mode operation conditions. table 38 - absolute maximum ratings parameter symbol value units case temperature under bias -40 to +85 c storage temperature t st -40 to +125 c supply voltage v dd1.8 -0.3 to + 3.6 v dc supply voltage v dd3.3 -0.3 to + 5.5 v dc voltage on any pin v in -0.3 to 5.5 v dc static discharge voltage 1000 v latch-up current 100 ma dc input current i in 20 ma lead temperature +230 c junction temperature t j +150 c notes on power supplies: 1. vdd3.3 should power up before vdd1.8. 2. vdd3.3 should not be allowed to drop below the vdd1.8 voltage level except when vdd1.8 is not powered.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 223 15 d.c. characteristics t a = -40c to +85c, v dd3.3 = 3.3v 8%, v dd1.8 = 1.8v 8% (typical conditions: t a = 25c, v dd3.3 = 3.3v, v dd1.8 = 1.8v) table 39 - d.c. characteristics symbol parameter min typ max units conditions vdd3.3 power supply 2.97 3.3 3.63 volts vdd1.8 power supply 1.65 1.8 1.95 volts vil input low voltage 0 0.8 volts guaranteed input low voltage vih input high voltage 2.0 volts guaranteed input high voltage vol output or bidirectional low voltage 0 0.1 0.4 volts vdd = min, iol = -4ma for d[7:0], laoe, recvclk1, recvclk2, recvclk3, tclk[3:1], tpos/tdat[3:1], tneg/tmfp[3:1], rgapclk/rsclk[3:1], rdatao[3:1], rfpo/rmfpo[3:1], rovrhd[3:1], tfpo/tmfpo/tgapclk[3:1], sbiact, iol = -8ma for sddata[7:0], sddp, sdpl, sdv5, sajust_req, sdc1fp, lac1j1v1, ladata[7:0], ladp, lapl, iol = -2ma for others. note 3
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 224 symbol parameter min typ max units conditions voh output or bidirectional high voltage 2.4 vdd3. 3 volts vdd = min, ioh = -4ma for d[7:0], laoe, recvclk1, recvclk2, recvclk3, tclk, tpos/tdat, tneg/tmfp, rgapclk/rsclk, rdatao, rfpo/rmfpo, rovrhd, tfpo/tmfpo/tgapclk, sbiact, ioh = -8ma for sddata[7:0], sddp, sdpl, sdv5, sajust_req, sdc1fp, lac1j1v1, ladata[7:0], ladp, lapl, ioh = -2ma for others. note 3 vt+ reset input high voltage 2.0 volts ttl schmidt vt- reset input low voltage 0.8 volts vth reset input hysteresis voltage tbd volts iilpu input low current +20 +100 a vil = gnd. notes 1, 3 iihpu input high current -10 +10 a vih = vdd. notes 1, 3 iil input low current -10 +10 a vil = gnd. notes 2, 3 iih input high current -10 +10 a vih = vdd. notes 2, 3 cin input capacitance 5 pf excluding package, package typically 2 pf cout output capacitance 5 pf excluding package, package typically 2 pf cio bidirectional capacitance 5 pf excluding package, package typically 2 pf iddop operating current 300 5 450 ma vdd1.8 = 1.94v vdd3.3 = 3.56 v outputs unloaded, telecom to sbi mode notes on d.c. characteristics: 1. input pin or bi-directional pin with internal pull-up resistor. 2. input pin or bi-directional pin without internal pull-up resistor.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 225 3. negative currents flow into the device (sinking), positive currents flow out of the device (sourcing).
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 226 16 microprocessor interface timing characteristics (t a = -40c to +85c, v dd3.3 = 3.3v 8%, v dd1.8 = 1.8v 8%) table 40 - microprocessor interface read access symbol parameter min max units tsar address to valid read set-up time 10 ns thar address to valid read hold time 5 ns tsalr address to latch set-up time 10 ns thalr address to latch hold time 10 ns tvl valid latch pulse width 20 ns tslr latch to read set-up 0 ns thlr latch to read hold 5 ns tprd valid read to valid data propagation delay 30 ns tzrd valid read negated to output tri-state 20 ns tzinth valid read negated to output tri-state 50 ns
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 227 figure 42: microprocessor interface read timing intb tz inth (csb+rdb) valid data d[7:0] tp rd tz rd ts ar th ar valid address a [12:0] a le ts alr tv l ts lr th alr th lr notes on microprocessor interface read timing: 1. output propagation delay time is the time in nanoseconds from the 1.4 volt point of the reference signal to the 1.4 volt point of the output. 2. maximum output propagation delays are measured with a 100 pf load on the microprocessor interface data bus, (d[7:0]). 3. a valid read cycle is defined as a logical or of the csb and the rdb signals. 4. in non-multiplexed address/data bus architectures, ale should be held high so parameters tsalr, thalr, tvl, and tslr are not applicable.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 228 5. parameter thar is not applicable if address latching is used. 6. when a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock. 7. when a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock. table 41 - microprocessor interface write access symbol parameter min max units tsaw address to valid write set-up time 10 ns tsdw data to valid write set-up time 20 ns tsalw address to latch set-up time 10 ns thalw address to latch hold time 10 ns tvl valid latch pulse width 20 ns tslw latch to write set-up 0 ns thlw latch to write hold 5 ns thdw data to valid write hold time 5 ns thaw address to valid write hold time 5 ns tvwr valid write pulse width 40 ns
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 229 figure 43: microprocessor interface write timing th dw valid data d[7:0] tv wr ts aw th aw ts dw (csb+wrb) a [12:0] valid address a le tv l ts alw ts lw th alw th lw notes on microprocessor interface write timing: 1. a valid write cycle is defined as a logical or of the csb and the wrb signals. 2. in non-multiplexed address/data bus architectures, ale should be held high so parameters tsalw, thalw, tvl, tslw and thlw are not applicable. 3. parameter thaw is not applicable if address latching is used. 4. when a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock. 5. when a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 230 17 temap-84 timing characteristics (t a = -40c to +85c v dd3.3 = 3.3v 8%, v dd1.8 = 1.8v 8%) table 42 - rstb timing symbol description min max units tvrstb rstb pulse width 100 ns figure 44 - rstb timing rstb tv rstb table 43 - ds3/e3 transmit interface timing symbol description min max units f ticlk ticlk[3:1] frequency 52 mhz t0 ticlk ticlk[3:1] minimum pulse width low 7.7 ns t1 ticlk ticlk[3:1] minimum pulse width high 7.7 ns ts tfpi tfpi/tmfpi[x] to ticlk[x] set-up time (loopt=0, active ticlk edge set by tdatifall bit) tfpi/tmfpi[x] to rclk[x] set-up time (loopt=1) 5 5 ns th tfpi tfpi/tmfpi[x] to ticlk[x] hold time (loopt=0, active ticlk edge set by tdatifall bit) tfpi/tmfpi[x] to rclk[x] hold time (loopt=1) 1 1 ns ts tdati tdati[x] to ticlk[x] set-up time (loopt = 0, active ticlk edge set by 5ns
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 231 tdatifall bit) tdati[x] to rclk[x] set-up time (loopt = 1) 5 th tdati tdati[x] to ticlk[x] hold time (loopt = 0, active ticlk edge set by tdatifall bit) tdati[x] to rclk[x] hold time (loopt = 1) 1 1 ns tp tgap ticlk[x] to tgapclk[x] prop delay (loopt = 0) rclk[x] to tgapclk[x] prop delay (loopt = 1) 2 2 10 10 ns tp tfpo ticlk[x] to tfpo/tmfpo[x] prop delay (loopt = 0, active ticlk edge set by tdatifall bit) rclk[x] to tfpo/tmfpo[x] prop delay (loopt = 1) 2 2 12 12 ns ts tgap tdati[x] to tgapclk[x] set-up time 2 ns th tgap tdati[x] to tgapclk[x] hold time 2 ns tp tclk ticlk[x] edge to tclk[x] edge prop delay 2 13 ns tp tpos tclk[x] edge to tpos/tdat[x] prop delay -1 4 ns tp tneg tclk[x] edge to tneg/tmfp[x] prop delay -1 4 ns tp tpos2 ticlk[x] high to tpos/tdat[x] prop delay 2 13 ns tp tneg2 ticlk[x] high to tneg/tmfp[x] prop delay 2 13 ns note: the ?[x]? implies the parameters for a data signal are only in relation to the associated clock. figure 62 - ds3/e3 transmit interface timing ts tfpi th tfpi tfpi/tmfpi ticlk/rclk
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 232 ts tdati th tdati tdati ticlk/rclk tp tfpo tfpo/tmfpo ticlk/rclk tp tgap tgapclk t iclk/rclk tp tgap ts tgap th tgap tdati tgapclk
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 233 t p tneg tneg/tmfp ticlk t p tpos tpos/tdat tclk ticlk=0, trise=0 t p tneg tneg/tmfp ticlk t p tpos tpos/tdat tclk ticlk=0, trise=1 t p tneg2 tneg/tmfp ticlk t p tclk t p tpos2 tpos/tdat tclk t p tclk ticlk=1, trise=x
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 234 table 44 - ds3/e3 receive interface timing symbol description min max units f rclk rclk[3:1] frequency 52 mhz t0 rclk rclk[3:1] minimum pulse width low 7.7 ns t1 rclk rclk[3:1] minimum pulse width high 7.7 ns ts rpos rpos/rdat[x] set-up time 4 ns th rpos rpos/rdat[x] hold time 1 ns ts rneg rneg/rlcv[x] set-up time 4 ns th rneg rneg/rlcv[x] hold time 1 ns tp rdato rsclk[x] edge to rdato[x] prop delay -1 4 ns tp rfpo rsclk[x] edge to rfpo/rmfpo[x] prop delay -1 4 ns tp rovrhd rsclk[x] edge to rovrhd[x] prop delay -1 4 ns tp rgap rgapclk[x] edge to rdato[x] prop delay -1 4 ns figure 63 - ds3/e3 receive interface timing ts rpos th rpos rpos/rdat rclk ts rneg th rneg rneg/rlcv
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 235 tp rdato rdato tp rfpo rfpo/rmfpo rsclk tp rovrhd rovrhd dashed line rsclk represents behaviour when rsclkr register bit = 1. tp rgap rdato rgapclk dashed line rsclk represents behaviour when rsclkr register bit = 1. notes on ds3/e3 interface timing: 1. when a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 236 2. when a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 volt point of the clock to the 1.4 volt point of the input. 3. output propagation delay time is the time in nanoseconds from the 1.4 volt point of the reference signal to the 1.4 volt point of the output. 4. maximum and minimum output propagation delays are measured with a 50 pf load on all the outputs. table 45 - line side telecom bus input timing ? 19.44 mhz (figure 67) symbol description min max units lrefclk frequency 19.44 -50 ppm 19.44 +50 ppm mhz lrefclk duty cycle 40 60 % lrefclk skew relative to srefclk -10 10 ns clk52m frequency (51.84 mhz) 51.84 -50 ppm 51.84 +50 ppm mhz clk52m frequency (44.928 mhz) 44.928 -50 ppm 44.928 +50 ppm mhz clk52m duty cycle 40 60 % ts tel all telecom bus inputs set-up time to lrefclk 5ns th tel all telecom bus inputs hold time to lrefclk 1ns line side telecom bus input timing - 77.76 mhz (figure 67) symbol description min max units lrefclk frequency 77.76 -50 ppm 77.76 +50 ppm mhz lrefclk duty cycle 40 60 % lrefclk skew relative to srefclk -5 5 ns
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 237 symbol description min max units clk52m frequency (51.84 mhz) 51.84 -50 ppm 51.84 +50 ppm mhz clk52m frequency (44.928 mhz) 44.928 -50 ppm 44.928 +50 ppm mhz clk52m duty cycle 40 60 % ts tel all telecom bus inputs set-up time to lrefclk 3ns th tel all telecom bus inputs hold time to lrefclk 0ns notes on telecom input timing: 1. when a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock. 2. when a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 volt point of the clock to the 1.4 volt point of the input. figure 64 - line side telecom bus input timing lrefcl k ts tel th tel lac1, lddata[7:0] lddp,ldp l ldv5,ldc1j1, ldtpl , ldai s
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 238 table 46 - telecom bus output timing - 19.44 mhz (figure 65 and figure 66) symbol description min max units t p tel lrefclk rising to all telecom bus outputs valid 320ns t z tel lrefclk rising to all telecom bus tristateable outputs going tristate 320ns t p teloe lrefclk rising to all telecom bus tristateable outputs going valid from tristate 013ns table 47 - telecom bus output timing ? 77.76 mhz (figure 65 and figure 66) symbol description min max units t p tel lrefclk rising to all telecom bus outputs valid 16 ns t z tel lrefclk rising to all telecom bus tristateable outputs going tristate 15 ns t p teloe lrefclk rising to all telecom bus tristateable outputs going valid from tristate 15 ns notes on telecom bus output timing: 1. output propagation delay time is the time in nanoseconds from the 1.4 volt point of the reference signal to the 1.4 volt point of the output. 2. maximum and minimum output propagation delays are measured with a 100 pf load on all the outputs. 3. output tristate delay is the time in nanoseconds from the 1.4 volt point of the reference signal to the point where the total current delivered through the output is less than or equal to the leakage current. 4. the propagation delay, t p tel , should be used when telecom bus outputs are always driven as configured by laddoe in register. the propagation delays, t p teloe and t z tel , should be used when the telecom bus outputs are multiplexed with other temap-84 devices using the tristate capability of the
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 239 outputs as configured by laddoe in register. note that under any specific operating condition, t z tel is guaranteed to be less than t p teloe . figure 65 - telecom bus output timing lrefclk ladata[7:0] ladp, lapl lav5,laoe tp tel lac1j1v1 figure 66 - telecom bus tristate output timing lrefclk tp teloe tz tel ladata[7:0] ladp, lapl lav5
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 240 table 48 - sbi add bus timing ? 19.44 mhz (figure 67) symbol description min max units srefclk frequency 19.44 -50 ppm 19.44 +50 ppm mhz srefclk duty cycle 40 60 % ts sbiadd all sbi add bus inputs set-up time to srefclk 4ns th sbiadd all sbi add bus inputs hold time to srefclk 0ns t p sbiadd srefclk to sajust_req valid 2 15 ns t z sbiadd srefclk to sajust_req tristate 2 15 ns
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 241 table 49 - sbi add bus timing ? 77.76 mhz (figure 67) symbol description min max units srefclk frequency 77.76 -50 ppm 77.76 +50 ppm mhz srefclk duty cycle 40 60 % ts sbiadd all sbi add bus inputs set-up time to srefclk 3ns th sbiadd all sbi add bus inputs hold time to srefclk 0ns t p sbiadd srefclk to sajust_req valid 1 6 ns t z sbiadd srefclk to sajust_req tristate 1 5 ns notes on sbi input timing: 1. when a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock. 2. when a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 volt point of the clock to the 1.4 volt point of the input.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 242 figure 67 - sbi add bus timing srefclk ts sbiadd th sbiadd sac1fp sadata[7:0] sadp,sapl sav5 sajust_req tp sbiadd tz sbiadd table 50 - sbi drop bus timing - 19.44 mhz (figure 65 figure 68) symbol description min max units t s sbidrop sdc1fp set-up time to srefclk 4 ns t h sbidrop sdc1fp hold time to srefclk 0 ns t p sbidrop srefclk to all sbi drop bus outputs valid 215ns t z sbidrop srefclk to all sbi drop bus outputs tristate 215ns t p outen sbidet[1] and sbidet[0] low to all sbi drop bus outputs valid 012ns t z outen sbidet[1] and sbidet[0] high to all sbi drop bus outputs tristate 012ns ts det sbidet[n] set-up time to srefclk 4 ns th det sbidet[n] hold time to srefclk 0 ns
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 243 table 51 - sbi drop bus timing - 77.76 mhz (figure 68 to figure 69) symbol description min max units t s sbidrop sdc1fp set-up time to srefclk 3 ns t h sbidrop sdc1fp hold time to srefclk 0 ns t p sbidrop srefclk to all sbi drop bus outputs valid 16 ns t z sbidrop srefclk to all sbi drop bus outputs tristate 15 ns notes on sbi output timing: 1. output propagation delay time is the time in nanoseconds from the 1.4 volt point of the reference signal to the 1.4 volt point of the output. 2. maximum and minimum output propagation delays are measured with a 100 pf load on all the outputs. 3. output tristate delay is the time in nanoseconds from the 1.4 volt point of the reference signal to the point where the total current delivered through the output is less than or equal to the leakage current.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 244 figure 68 - sbi drop bus timing srefclk sdc1fp sddata[7:0] sddp, sdpl sdv5,sbiact tp s bidrop tz sbidrop sddata[7:0] sddp, sdpl sdv5 sdc1fp th sbidrop ts sbidrop figure 69 - sbi drop bus collision avoidance timing sbidet[n] tp outen tz outen sddata[7:0] sddp, sdpl sdv5 ts det srefclk th det
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 245 table 52 - egress flexible bandwidth port timing (figure 70) symbol description min max units efbwclk[n] frequency 0 52 mhz efbwclk[n] high phase 7 ns efbwclk[n] low phase 7 ns ts efbw efbwdreq[n] set-up time to efbwclk[n] rising edge 4ns th efbw efbwdreq[n] hold time to efbwclk[n] rising edge 0ns t p efbw efbwclk[n] falling edge to efbwdat[n] and efbwen[n] valid 215ns figure 70 - egress flexible bandwidth port timing efbwclk[n] efbwdreq[n] efbwdat[n], efbwen[n] ts th tp efbw efbw efbw
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 246 table 53 - ingress flexible bandwidth port timing (figure 71) symbol description min max units ifbwclk[n] frequency 0 52 mhz ifbwclk[n] high phase 7 ns ifbwclk[n] low phase 7 ns ts ifbw ifbwdat[n] and ifbwen[n] set- up time to ifbwclk[n] rising edge 4ns th ifbw ifbwdat[n] and ifbwen[n] hold time to ifbwclk[n] rising edge 1ns figure 71 - ingress flexible bandwidth port timing ifbwclk[n] ts th ifbw ifbw ifbwdat[n], ifbwen[n] notes on flexible bandwidth port timing: 1. when a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock. 2. when a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 volt point of the clock to the 1.4 volt point of the input. 5. output propagation delay time is the time in nanoseconds from the 1.4 volt point of the reference signal to the 1.4 volt point of the output. 6. maximum and minimum output propagation delays are measured with a 100 pf load on all the outputs.
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 247 table 54 - xclk input (figure 72) symbol description min max units t l xclk xclk_t1 and xclk_e1 low pulse width 4 8ns t h xclk xclk_t1 and xclk_e1 high pulse width 4 8ns t xclk xclk_t1 and e1_xlk period (typically 1/37.056 mhz 32 ppm for xclk_t1 and 1/49.152 mhz for xclk_e1) 20 ns figure 72 - xclk input timing xclk_t1 or xclk_e1 t l t h t xclk xclk xclk
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 248 table 55 - transmit line interface timing (figure 73) symbol description min max units ctclk frequency (must be integer multiple of 8 khz.) 0.008 2.048 mhz t h ctclk ctclk high duration 60 ns t l ctclk ctclk low duration 60 ns figure 73 - transmit line interface timing ctclk t l t h t ctclk ctclk ctclk notes on ingress and egress serial interface timing: 1. high pulse width is measured from the 1.4 volt points of the rise and fall ramps. low pulse width is measured from the 1.4 volt points of the fall and rise ramps. 2. when a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock. 3. when a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 volt point of the clock to the 1.4 volt point of the input. 4. setup, hold, and propagation delay specifications are shown relative to the default active clock edge, but are equally valid when the opposite edge is selected as the active edge. 5. output propagation delay time is the time in nanoseconds from the 1.4 volt point of the reference signal to the 1.4 volt point of the output. 6. output propagation delays are measured with a 50 pf load on all outputs with the exception of the high speed ds3/e3 outputs (tclk[3:1],
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 249 tpos/tdat[3:1], tneg/tmfp[3:1]). the tclk[3:1], tpos/tdat[3:1], tneg/tmfp[3:1] output propagation delays are measured with a 20 pf load. table 56 - remote serial alarm port timing symbol description min max units radeastck and radwestck frequency 1.344 10 mhz radeastck and radwestck duty cycle 40 60 % t h radfp radeastfp and radwestfp hold time 5ns t s radfp radeastfp and radwestfp setup time 5ns t h rad radeast and radwest hold time 5 ns t s rad radeast and radwest setup time 5 ns figure 74 - remote serial alarm port timing radeastck/ radwestck radeastfp/ radwestfp radeast/ radwest ts radfp th radfp ts rad th rad
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 250 table 57 - jtag port interface symbol description min max units tck frequency 1 mhz tck duty cycle 40 60 % ts tms tms set-up time to tck 50 ns th tms tms hold time to tck 50 ns ts tdi tdi set-up time to tck 50 ns th tdi tdi hold time to tck 50 ns tp tdo tck low to tdo valid 2 50 ns tv trstb trstb pulse width 100 ns
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 251 figure 75 - jtag port interface timing ts tms th tms tms tck ts tdi th tdi tdi tp tdo tdo tck trstb tv trstb
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 252 18 ordering and thermal information table 58 - ordering information part no. description PM5366-pi 324 plastic ball grid array (pbga) table 59 - thermal information ? theta ja vs. airflow forced air (linear feet per minute) theta ja ( c/w) @ specified power convection 100 200 300 400 500 dense board 39.4 35.1 32.0 30.0 28.6 27.7 jedec board 22.1 20.4 19.2 18.4 17.9 17.4
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 253 19 mechanical information figure 76 - 324 pin pbga 23x23mm body e a b c d e f g h j k l m n p r t u v w y aa ab b bottom view a1 ball corner j i "d" dia. 3 places 1 3 5 7 9 11 13 15 17 19 21 2 4 6 8 10 12 14 16 18 20 22 m m 0.30 c b 0.10 c a b a a1 ball indicator d d1 e1 e 0.20 (4x) 45 chamfer 4 places a1 ball pad corner top view a1 a c a2 seating plane bbb c c aaa c 30 typ side view notes: 1) all dimensions in millimeter. 2) dimension aaa denotes coplanarity. 3) dimension bbb denotes parallel. 23.00 19.00 19.50 20.20 1.00 1.00 0.63 0.50 0.70 2.07 2.28 2.49 1.82 2.03 2.22 0.40 0.50 0.60 1.12 1.17 1.22 23.00 19.00 19.50 20.20 0.36 0.61 1.00 1.00 0.15 0.35 0.30 0.40 0.55 0.67
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer proprietary and confidential 254 notes
preliminary PM5366 temap-84 datasheet pmc- 2010672 issue 1 high density 84/63 channel vt/tu mapper and m13 multiplexer none of the information contained in this document constitutes an express or implied warranty by pmc-sierra, inc. as to the suf ficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merc hantab ility, performance, compatibility with other parts or systems, of any of the products of pmc-sierra, inc., or any portion thereof, referred to in this document. pmc-sierra, inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not l imited to, express and implied warranties of accuracy, completeness, merchantab ility, fitness for a particular use, or non-infringement. in no event will pmc-sierra, inc. be liable for any direct, indirect, special, inci dental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not pmc-sierra, inc. has been advised of the possibility of such damage. ? 2001 pmc-sierra, inc. pmc-2010672 (p1) issue date: april 2001 pmc-sierra, inc. 105 - 8555 baxter place burnaby, bc canada v5a 4v7 _604 .415.6000 contacting pmc-sierra, inc. pmc-sierra, inc. 105-8555 baxter place burnaby, bc canada v5a 4v7 tel: (604) 415-6000 fax: (604) 415-6200 document information: document@pmc-sierra.com corporate information: info@pmc-sierra.com application information: apps@pmc-sierra.com web site: http://www.pmc-sierra.com

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